Texas Instruments TMS320C6A816 Series Technical Reference Manual page 868

Registers
Table 7-9. I2C Status Register (I2C_IRQSTATUS) Field Descriptions (continued)
Bit Field
5 GC
4 XRDY
3 RRDY
2 ARDY
1 NACK
0 AL
868
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Value Description
General call IRQ enabled status. Set to '1' by core when General call address detected and
interrupt signaled to MPUSS. Write '1' to clear.
0 No general call detected
1 General call address detected
Transmit data ready IRQ enabled status. Set to '1' by core when transmitter and when new
data is requested. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to
clear.
0 Transmision ongoing
1 Transmit data ready
Receive data ready IRQ enabled status. Set to '1' by core when receiver mode, a new data is
able to be read. When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear.
0 No data available
1 Receive data available
Register access ready IRQ enabled status. When set to '1' it indicates that previous access
has been performed and registers are ready to be accessed again. An interrupt is signaled to
MPUSS. Write '1' to clear.
0 Module busy
1 Access ready
No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been
received, an interrupt is signaled to MPUSS. Write '1' to clear this bit.
0 Normal operation
1 Not Acknowledge detected
Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses
the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it
always returns 0.
0 Normal operation
1 Arbitration lost detected
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SPRUGX9 – 15 April 2011
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