Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1450

Registers
Table 14-66. CM_HDDSS_CLKSTCTRL Register Field Descriptions (continued)
Bit Field
8 CLKACTIVITY_HD_VENC_D_GCLK
7-2 Reserved
1-0 CLKTRCTRL
1450
Power, Reset, and Clock Management (PRCM) Module
Preliminary
Value Description
This field indicates the state of the HD_VENC_D_GCLK
clock in the domain.
0 Corresponding clock is gated
1 Corresponding clock is active
0 Reserved
Controls the clock state transition of the HD-DSS clock
domain.
0 Reserved
1h SW_SLEEP: Start a software forced sleep transition on
the domain.
2h SW_WKUP: Start a software forced wake-up transition
on the domain.
3h Reserved
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SPRUGX9 – 15 April 2011
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