Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1479

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Table 14-96. CM_ALWON_L3_SLOW_CLKSTCTRL Register Field Descriptions (continued)
Bit Field
8 CLKACTIVITY_L3_SLOW_GCLK
7-2 Reserved
1-0 CLKTRCTRL
SPRUGX9 – 15 April 2011
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Preliminary
Value Description
This field indicates the state of the L3_SLOW_GCLK clock in
the domain.
0 Corresponding clock is gated
1 Corresponding clock is active
0 Reserved
Controls the clock state transition of the L3_SLOW clock
domain in Always ON power domain.
0 Reserved
1h SW_SLEEP: Start a software forced sleep transition on the
domain.
2h SW_WKUP: Start a software forced wake-up transition on the
domain.
3h Reserved
Power, Reset, and Clock Management (PRCM) Module
© 2011, Texas Instruments Incorporated
Registers
1479