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Architecture
It is not recommended to put the overflow value (FFFF FFFFh) in TLDR because it can lead to
undesired results.
An interrupt can be issued on overflow if the overflow interrupt enable bit is set in the timer Interrupt
Enable Register (IRQENABLE_SET OVF_IT_FLAG bit = 1). A dedicated output pin (PORTIMERPWM)
is programmed through TCLR (TRG and PT bits) to generate one positive pulse (prescaler duration) or
to invert the current value (toggle mode) when an overflow occurs.
0x0000 0000
Load register
(TLDR)
17.2.1.2 Capture Mode Functionality
The timer value in TCRR can be captured and saved in TCAR1 or TCAR2 function of the mode
selected in TCLR through the field CAPT_MODE when a transition is detected on the module input pin
(PIEVENTCAPT). The edge detection circuitry monitors transitions on the input pin (PIEVENTCAPT).
Rising transition, falling transition or both can be selected in TCLR (TCM bit) to trig the timer counter
capture. The module sets the IRQSTATUS ( TCAR_IT_FLAG bit) when an active transition is detected
and at the same time the counter value TCRR is stored in one of the timer capture registers TCAR1 or
TCAR2 as follows:
•
If TCLR's CAPT_MODE field is 0 then, on the first enabled capture event, the value of the counter
register is saved in TCAR1 register and all the next events are ignored (no update on TCAR1 and
no interrupt triggering) until the detection logic is reset or the interrupt status register is cleared on
TCAR's position writing a 1 in it.
•
If TCLR's CAPT_MODE field is 1 then, on the first enabled captured event, the counter value is
saved in TCAR1 register and, on the second enabled capture event, the value of the counter
register is saved in TCAR2 register. All the other events are ignored (no update on TCAR1/2 and no
interrupt triggering) until the detection logic is reset or the interrupt status register is cleared on
TCAR's position writing a 1 in it. This mechanism is useful for period calculation of a clock if that
clock is connected to the PIEVENTCAPT input pin.
The edge detection logic is reset (a new capture is enabled) when the active capture interrupt is served
- TCAR_IT_FLAG bit of IRQSTATUS (previously 1) is cleared. The timer functional clock (input to
prescaler) is used to sample the input pin (PIEVENTCAPT). Input negative or positive pulse can be
detected when pulse time is above functional clock period. An interrupt can be issued on transition
detection if the capture interrupt enable bit is set in the Timer Interrupt Enable Register
IRQENABLE_SET (TCAR_IT_FLAG bit).
In
Figure
17-3, the TCM value is 01 and CAPT_MODE is 0 - only rising edge of the PIEVENTCAPT will
trigger a capture in TCAR and only TCAR1 will update.
In
Figure
17-4, the TCM value is 01 and CAPT_MODE is 1 - only rising edge of the PIEVENTCAPT will
trigger a capture in TCAR1 on first enabled event and TCAR2 will update on the second enabled event.
1636
Timers
Preliminary
Figure 17-2. TCRR Timing Value
Trig Register
(TTGR)
Counter register
(TCRR)
Auto-reload on
(TCLR (AR) = 1)
© 2011, Texas Instruments Incorporated
www.ti.com
0xFFFF FFFF
Overflow
pulse is generated
SPRUGX9 – 15 April 2011
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