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Architecture
18.2.12 Watchdog Timers Under Emulation
During emulation mode, the watchdog timer can/cannot continue running, according to the value of the
WDT_WDSC[5] EMUFREE bit of the system configuration register (WDT_WDSC).
•
When EMUFREE is 1, watchdog timer execution is not stopped and a reset pulse is still generated
when overflow is reached.
•
When EMUFREE is 0, the counters (prescaler/timer) are frozen and incrementation restarts after
exiting from emulation mode.
18.2.13 Accessing Watchdog Timer Registers
Posted/nonposted selection applies only to functional registers that require synchronization on/from the
timer functional clock domain (WDTi_FCLK). For write/read operation, the following registers are
affected:
•
WDT_WCLR
•
WDT_WCRR
•
WDT_WLDR
•
WDT_WTGR
•
WDT_WDLY
•
WDT_WSPR
The timer interface clock domain synchronous registers are not affected by the posted/nonposted
selection; the write/read operation is effective and acknowledged (command accepted) after one
WDT_ICLK cycle from the command assertion. The timer interface clock domain synchronous registers
are:
•
WDT_WIDR
•
WDT_WDSC
•
WDT_WDST
•
WDT_WIRQSTATRAW
•
WDT_WIRQSTAT
•
WDT_WIRQENSET
•
WDT_WIRQENCLR
•
WDT_WWPS
NOTE: Accesses to WDT2 and WDT3 are posted.
1666
Watchdog Timer
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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