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PCIe recognizes four address spaces, Memory, I/O, Configuration, and Message. Messages do not
consume any Memory or I/O resource and no type of translation is required. I/O addressing is used by
PCIe (only supported in RC configuration) in outbound access to a Legacy EP; this is not a mandatory
feature by PCIe and when supported the I/O spaces is memory mapped to system memory. This
implies that there exists a need to map only two types of device address spaces, Configuration and
Memory address spaces. The address translators apply to translating Configuration and Memory
addresses between PCIe address and OCP/Internal address.
The address space of the physical device is divided into two spaces (Range 0 and Range 1). Address
space (Range 0) that is used for PCI configuration tasks, referred to as configuration space; and a
second Address space (Range 1) that is used for accessing memory (non-configuration related),
referred to as memory space.
NOTE: All I/O access use Address Routing. There is no-support for I/O access in Inbound
direction. That is, when it comes to a transaction that performs I/O access only TLPs with
Outbound transactions are supported.
13.2.3.1 Outbound Address Translations
Outgoing Transaction Layer Packets (TLP) associated with "Address Routing" would require the use of
the Outbound address translator that creates a mapping between the OCP/Internal memory/address
and external PCIe device memory/address on the PCIe fabric.
The PCIE Subsystem allows mapping of Physical device address to PCIe address on outgoing TLPs.
This is accomplished by using outbound address translation logic. For each outbound read/write
request, the address translation module within PCIESS converts an OCP address (OCP/Internal
address) to a PCIE address (PCIe address) of Memory Read/Write type. The address translation logic
uses information programmed within address translation registers to perform the mapping. The
registers, OB_SIZE, OB_OFFSET_INDEXn, OB_OFFSETn_HI are used in conjunction with Out-bound
address translator.
The physical memory range that PCIESS occupies in the devices internal address range is divided into
32 equally sized translation regions (Regions 0 to 31). These equally divided regions can be
programmed to have a size of 1, 2, 4, or 8 MB and this size value is communicated with the Outbound
Address Translator via the OB_SIZE register. Each such region (OCP/Internal address) can be
remapped to a PCIE address range of same size as the size of translation region itself. The address
translation logic identifies and extract the 5 bits (32 regions) from the OCP/Internal address and uses
this value as an index to identify one of the 32 regions. The bit address position for these 5 bits
depends on the size of the regions. Once the region is identified, the Address translation logic then
generates PCIe base address, from the values provided within the corresponding configuration
registers for that region, that is, the registers OB_OFFSET_INDEXn and OB_OFFSETn_HI [n = 0-31]. If
32-bit addressing is used, OB_OFFSETn_HI will always be programmed with zero.
Once the PCIe base address has been identified, the offset that is to be added to this base address is
derived from the lower bit fields of the OCP/Internal address and the bit fields that make up this offset
correspond to the size of the regions.
Application software is required to identify the desired physical memory that is to be accessible by the
PCIe module and initialize the corresponding registers prior to enabling PCIe transactions. For
Outbound translation the registers in use, initialization, and usage is discussed below.
•
Outbound Size Register (OB_SIZE) — Application software initializes this register with the size
value that applies to all 32 regions. OB_SIZE=0,1,2, and 3 correspond to region sizes of 1MB, 2MB,
4MB, and 8MB and the corresponding indexed regions for these sizes are identified from the
OCP/Internal address. Bits[2four:20], bits [25:21], bits[26:22], and bits[27:23] of the OCP/Internal
address holds the Index value used to identify one of the 32 regions for the 1MB, 2MB, fourMB and
8MB regions respectively. Size of regions also affect the meaningful bit fields within
OB_OFFSET_INDEXn [n=0-31] register. The lower bit fields corresponding to the size of the region
are masked and not used in the mapping.
SPRUGX9 – 15 April 2011
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Preliminary
Peripheral Component Interconnect Express (PCIe)
© 2011, Texas Instruments Incorporated
Architecture
1277
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