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9.2.4.1
Interrupt-Driven Operation
An interrupt enable bit must be set in the SD_IE register to enable the module internal source of
interrupt.
When an interrupt event occurs, the single interrupt line is asserted and the LH must:
•
Read the SD_STAT register to identify which event occurred.
•
Write 1 into the corresponding bit of the SD_STAT register to clear the interrupt status and release
the interrupt line (if a read is done after this write, this would return 0).
NOTE: In the SD_STAT register, Card Interrupt (CIRQ) and Error Interrupt (ERRI) bits cannot be
cleared.
The SD_STAT[8] CIRQ status bit must be masked by disabling the SD_IE[8]
CIRQ_ENABLE bit (cleared to 0), then the interrupt routine must clear SDIO interrupt
source in SDIO card common control register (CCCR).
The SD_STAT[15] ERRI bit is automatically cleared when all status bits in
SD_STAT[31:16] are cleared.
9.2.4.2
Polling
When the interrupt capability of an event is disabled in the SD_ISE register, the interrupt line is not
asserted:
•
Software can poll the status bit in the SD_STAT register to detect when the corresponding event
occurs.
•
Writing 1 into the corresponding bit of the SD_STAT register clears the interrupt status and does not
affect the interrupt line state.
NOTE: Please see the note in
9.2.5 DMA Modes
The device supports DMA slave mode only. In this case, the controller is slave on DMA transaction
managed by two separated requests (SDMAWREQN and SDMARREQN)
9.2.5.1
DMA Slave Mode Operations
The SD/SDIO controller can be interfaced with a DMA controller. At system level, the advantage is to
discharge the local host (LH) of the data transfers. The module does not support wide DMA access
(above 1024 bytes) for SD cards as specified in the SD Card Specificationand SD Host Controller
Standard Specification.
The DMA request is issued if the following conditions are met:
•
The SD_CMD[0] DE bit is set to 1 to trigger the initial DMA request (the write must be done when
running the data transfer command).
•
A command was emitted on the SD_cmd line.
•
There is enough space in the buffer of the SD/SDIO controller to write an entire block (BLEN writes).
SPRUGX9 – 15 April 2011
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Preliminary
Section 9.2.4.1
concerning CIRQ and ERRI bits clearing.
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
© 2011, Texas Instruments Incorporated
Architecture
939
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