Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1003

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Table 9-36. Capabilities Register (SD_CAPA) Field Descriptions (continued)
Bit Field
21 HSS
20 Reserved
19 AD2S
18 Reserved
17-16 MBL
15-14 Reserved
13-8 BCF
7 TCU
6 Reserved
5-0 TCF
SPRUGX9 – 15 April 2011
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Preliminary
Value Description
High-speed support. This bit indicates that the host controller supports high speed operations
and can supply an up-to-52 MHz clock to the card.
Read 0 DMA not supported
Read 1 DMA supported
0 Reserved bit field. Do not write any value.
This bit indicates whether the Host Controller is capable of using ADMA2. It depends on
setting of generic parameter MADMA_EN.
Read 0 ADMA2 supported
Read 1 ADMA2 not supported
0 Reserved bit field. Do not write any value.
Maximum block length. This value indicates the maximum block size that the host driver can
read and write to the buffer in the host controller.
The host controller supports 512 bytes and 1024 bytes block transfers.
Read 0 512 bytes
Read 1 1024 bytes
Read 2 2048 bytes
0 Reserved bit field. Do not write any value.
Base clock frequency for clock provided to the card.
Read 0 The value indicating the base (maximum) frequency for the output clock provided to the card
is system dependent and is not available in this register. Get the information via another
method. See the Power Reset and Clock Management chapter for more information on the
value of FUNC_96M_CLK clock signal.
Timeout clock unit. This bit shows the unit of base clock frequency used to detect Data
Timeout Error (SD_STAT[20] DTO bit).
Read 0 kHz
Read 1 MHz
0 Reserved. This bit is initialized to zero, and writes to it are ignored.
Timeout clock frequency. The timeout clock frequency is used to detect Data Timeout Error
(SD_STAT[20] DTO bit).
Read 0 The timeout clock frequency depends on the frequency of the clock provided to the card. The
value of the timeout clock frequency is not available in this register.
© 2011, Texas Instruments Incorporated
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Registers
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