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11.2.8.6.14 Set the Transmit Frame-Sync Polarity
The FSXP bit (PCR_REG[3]) determines whether frame–synchronization pulses are active high or
active low on the McBSP.FSX pin.
Transmit frame–synchronization pulses can be generated internally by the sample rate generator or
driven by an external source. The source of frame synchronization is selected by programming the
PCR_REG[11] register FSXM mode bit. FSX is also affected by the FSGM bit (SRGR2_REG[12]).
Similarly, transmit clocks can be selected to be inputs or outputs by programming the PCR_REG[9]
register CLKXM mode bit.
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame–synchronization pulses), the
McBSP detects them on the internal falling edge of clock, internal CLKR, and internal CLKX,
respectively. The receive data arriving at the McBSP.DR pin is also sampled on the falling edge of
internal CLKR. These internal clock signals are either derived from external source via CLK(R/X) pins
or driven by the sample rate generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data
on the McBSP.DX pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR_REG) configure the polarities of the
FSR, FSX, CLKR, and CLKX signals, respectively. All frame–synchronization signals (internal FSR,
internal FSX) that are internal to the serial port are active high. If the serial port is configured for
external frame synchronization (FSR/FSX are inputs to McBSP) and FSRP = FSXP = 1, the external
active–low frame–synchronization signals are inverted before being sent to the receiver (internal FSR)
and transmitter (internal FSX). Similarly, if internal synchronization (FSR/FSX are output pins and
GSYNC = 0) is selected and the polarity bit FS(R/X)P = 1, the internal active–high
frame–synchronization signals are inverted before being sent to the FS(R/X) pin.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP = 1 and
external clocking is selected (CLKXM = 0 and CLKX is an input), the external falling–edge triggered
input clock on CLKX is inverted to a rising–edge triggered clock before being sent to the transmitter. If
CLKXP = 1, and internal clocking selected (CLKXM = 1 and CLKX is an output pin), the internal
(rising–edge triggered) clock, internal CLKX, is inverted before being sent out on the McBSP.CLKX pin.
Similarly, the receiver can reliably sample data that is clocked with a rising edge clock (by the
transmitter). The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The
receive data is always sampled on the falling edge of internal CLKR. Therefore, if CLKRP = 1 and
external clocking is selected (CLKRM = 0 and CLKR is an input pin), the external rising–edge triggered
input clock on CLKR is inverted to a falling–edge triggered clock before being sent to the receiver. If
CLKRP = 1 and internal clocking is selected (CLKRM = 1), the internal falling–edge triggered clock is
inverted to a rising–edge triggered clock before being sent out on the McBSP.CLKR pin.
Note that CLKRP = CLKXP in a system where the same clock (internal or external) is used to clock the
receiver and transmitter. The receiver uses the opposite edge as the transmitter to ensure valid setup
and hold of data around this edge.
11.2.8.6.15 Set the SRG Frame-Sync Period and Pulse Width
FPER bit field (SRGR2_REG[11:0]) is used to set the SRG frame-sync period and FWID bit field
(SRGR1_REG[15:8]) is used to set the SRG pulse width. The sample rate generator can produce a
clock signal, CLKG, and a frame–synchronization signal, FSG. If the sample rate generator is supplying
receive or transmit frame synchronization, you must program the bit fields FPER and FWID.
On FSG, the period from the start of a frame–synchronization pulse to the start of the next pulse is
(FPER + 1) CLKG cycles. The 12 bits of FPER allow a frame–synchronization period of 1 to 4096
CLKG cycles, which allows up to 4096 data bits per frame. When GSYNC = 1, FPER is a don't care
value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of FWID allow a pulse width
of 1 to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the
programmed word length.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Architecture
1171
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