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Table 7-8. I2C Status Raw Register (I2C_IRQSTATUS_RAW) Field Descriptions (continued)
Bit
Field
Value
13
RDR
0
1
12
BB
0
1
11
ROVR
0
1
10
XUDF
0
1
SPRUGX9 – 15 April 2011
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Preliminary
Description
Receive draining IRQ status. I2C Receive mode only.
This read/clear only bit is set to 1 when the module is configured as a receiver, a stop condition was
received on the bus and the RX FIFO level is below the configured threshold (RXTRSH). When this bit
is set to 1 by the core, CPU must read the I2C_BUFSTAT.RXSTAT register in order to check the
amount of data left to be transferred from the FIFO. Then, according to the mode set (DMA or
interrupt), the CPU needs to enable the draining feature of the DMA controller with the number of data
bytes to be transferred (I2C_BUFSTAT.RXSTAT), or generate read data accesses according to this
value (IRQ mode). The interrupt needs to be cleared after the DMA controller was reconfigured (if DMA
mode enabled), or before generating data accesses to the FIFO (if IRQ mode enabled).
If the corresponding interrupt was enabled, an interrupt is signaled to the local host. The CPU can also
poll this bit. For more details about RDR generation, refer to the FIFO Management subsection.
The CPU can only clear this bit by writing a 1 into this register. A write 0 has no effect.
Receive draining inactive
Receive draining enabled
Value after reset is low.
This read-only bit indicates the state of the serial bus.
In slave mode, on reception of a start condition, the device sets BB to 1. BB is cleared to 0 after
reception of a stop condition.
In master mode, the software controls BB. To start a transmission with a start condition, MST, TRX,
and STT must be set to 1 in the I2C_CON register. To end a transmission with a stop condition, STP
must be set to 1 in the I2C_CON register. When BB = 1 and STT = 1, a restart condition is generated.
Bus is free
Bus is occupied
Value after reset is low.
Receive overrun status. Writing into this bit has no effect. I2C receive mode only.
This read-only bit indicates whether the receiver has experienced overrun. Overrun occurs when the
shift register is full and the receive FIFO is full. An overrun condition does not result in a data loss; the
peripheral is just holding the bus (low on SCL) and prevents other bytes from being received.
ROVR is set to 1 when the I2C has recognized an overrun. ROVR is clear when reading I2C_DATA
register, or when resetting the I2C (I2C_CON:I2C_EN = 0).
Normal operation
Receiver overrun
Value after reset is low.
Transmit underflow status. Writing into this bit has no effect. I2C transmit mode only.
This read-only bit indicates whether the transmitter has experienced underflow. In master transmit
mode, underflow occurs when the shift register is empty, the transmit FIFO is empty, and there are still
some bytes to transmit (DCOUNT
In slave transmit mode, underflow occurs when the shift register is empty, the transmit FIFO is empty,
and there are still some bytes to transmit (read request from external I2C master).
XUDF is set to 1 when the I2C has recognized an underflow. The core holds the line till the underflow
cause has disappeared.
XUDF is clear when writing I2C_DATA register or resetting the I2C (I2C_CON:I2C_EN = 0).
Normal operation
Transmit underflow
Value after reset is low.
© 2011, Texas Instruments Incorporated
0).
Inter-Integrated Circuit (I2C) Controller Module
Registers
863
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