Texas Instruments TMS320C6A816 Series Technical Reference Manual page 991

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Table 9-32. Interrupt Status Register (SD_STAT) Field Descriptions (continued)
Bit Field
25 ADMAE
24 ACE
23 Reserved
22 DEB
21 DCRC
20 DTO
19 CIE
SPRUGX9 – 15 April 2011
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Preliminary
Value Description
ADMA Error. This bit is set when the Host Controller detects errors during ADMA based data
transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status
Register. In addition, the Host Controller generates this interrupt when it detects invalid
descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status
indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not
set at the error descriptor.
Read 0 No interrupt
Write 0 Status bit unchanged
Read 1 ADMA error
Write 1 Status is cleared.
Auto CMD12 error. This bit is set automatically when one of the bits in Auto CMD12 Error
status register has changed from 0 to 1.
Read 0 No error
Write 0 Status bit unchanged
Read 1 AutoCMD12 error
Write 1 Status is cleared.
0 Reserved bit field. Do not write any value
Data End Bit error. This bit is set automatically when detecting a 0 at the end bit position of
read data on SD_DAT line or at the end position of the CRC status in write mode.
Read 0 No error
Write 0 Status bit unchanged
Read 1 Data end bit error
Write 1 Status is cleared.
Data CRC Error. This bit is set automatically when there is a CRC16 error in the data phase
response following a block read command or if there is a 3-bit CRC status different of a
position "010" token during a block write command.
Read 0 No error
Write 0 Status bit unchanged
Read 1 Data CRC error
Write 1 Status is cleared.
Data timeout error. This bit is set automatically according to the following conditions:
• Busy timeout for R1b, R5b response type
• Busy timeout after write CRC status
• Write CRC status timeout
• Read data timeout
Read 0 No error
Write 0 Status bit unchanged
Read 1 Time out
Write 1 Status is cleared.
Command index error. This bit is set automatically when response index differs from
corresponding command index previously emitted. It depends on the enable bit (SD_CMD[20]
CICE).
Read 0 No error
Write 0 Status bit unchanged
Read 1 Command index error
Write 1 Status is cleared.
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Registers
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