Command Token Format - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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9.2.1.2
Protocol and Data Format
The bus protocol between the SD/SDIO host controller and the card is message-based. Each message
is represented by one of the following parts:
Command: A command starts an operation. The command is transferred serially from the SD/SDIO
host controller to the card on the SD_CMD line.
Response: A response is an answer to a command. The response is sent from the card to the
SD/SDIO host controller. It is transferred serially on the SD_CMD line.
Data: Data are transferred from the SD/SDIO host controller to the card or from a card to the SD/SDIO
host controller using the DATA lines.
Busy: The SD_DAT0 signal is maintained low by the card as far as it is programming the data
received.
CRC status: CRC result is sent by the card through the SD_DAT0 line when executing a write transfer.
In the case of transmission error, occurring on any of the active data lines, the card sends a negative
CRC status on SD_DAT0. In the case of successful transmission, over all active data lines, the card
sends a positive CRC status on SD_DAT0 and starts the data programming procedure.
9.2.1.2.1 Protocol
The SD/SDIO interface only supports block-oriented operation.
There are specific commands for block-oriented operation. See the SD Memory Card Specifications
and the SDIO Card Specification, Part E1 for details about commands and programming sequences
supported by the SD and SDIO cards.
9.2.1.2.2 Data Format
Coding Scheme for Command Token
Command packets always start with 0 and end with 1. The second bit is a transmitter bit1 for a host
command. The content is the command index (coded by 6 bits) and an argument (for example, an
address), coded by 32 bits. The content is protected by 7-bit CRC checksum (see
0
SPRUGX9 – 15 April 2011
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Preliminary
Figure 9-3. Command Token Format
1
Content
48 bits length
© 2011, Texas Instruments Incorporated
CRC
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Architecture
Figure
9-3).
1
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