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20.3.1.1.4.3 TX Mode: Control Transfer of Peripheral Mode
When the endpoint is in TX state, all arriving IN tokens need to be treated as part of a data phase until
the required amount of data has been sent to the host. If either a SETUP or an OUT token is received
while the endpoint is in the TX state, this will cause a SETUPEND condition to occur as the core
expects only IN tokens.
Three events can cause TX mode to be terminated before the expected amount of data has been sent
as shown in
Figure
1. The host sends an invalid token causing a SETUPEND condition (bit 4 of PERI_CSR0 is set).
2. The firmware sends a packet containing less than the maximum packet size for Endpoint 0.
3. The firmware sends an empty data packet.
Until the transaction is terminated, the firmware simply needs to load the FIFO when it receives an
interrupt which indicates that a packet has been sent from the FIFO. An interrupt is generated when
TXPKTRDY is cleared.
When the firmware forces the termination of a transfer (by sending a short or empty data packet), it
should set the DATAEND bit of PERI_CSR0 (bit 3) to indicate to the core that the data phase is
complete and that the core should next receive an acknowledge packet.
Figure 20-5. Flow Chart of Transmit Data Stage of a Control Transfer in Peripheral Mode
SPRUGX9 – 15 April 2011
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Preliminary
20-5:
TX Mode
Write
MaxP Bytes
£
to FIFO
Last Packet
Yes
Set TxPktRdy
and Set DataEnd
State
IDLE
®
Return
© 2011, Texas Instruments Incorporated
No
Set TxPktRdy
Protocol Description(s)
1767
Universal Serial Bus (USB)
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