System Configuration Register (Sd_Sysconfig); System Configuration Register (Sd_Sysconfig) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

9.4.4 System Configuration Register (SD_SYSCONFIG)

This register allows controlling various parameters of the OCP interface. The system configuration
register (SD_SYSCONFIG) is shown in
31
15 14
Reserved
R-0
7
Reserved
R-0
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
Table 9-14. System Configuration Register (SD_SYSCONFIG) Field Descriptions
Bit Field
31-14 Reserved
13-12 STANDBYMODE
11-10 Reserved
9-8 CLOCKACTIVITY
7-5 Reserved
4-3 SIDLEMODE
964
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Figure 9-32
Figure 9-32. System Configuration Register (SD_SYSCONFIG)
13 12
STANDBYMODE
R/W-2h
5 4
SIDLEMODE
Value Description
0 These bits are initialized to zero, and writes to them are ignored. Reads return 0.
Master interface power Management, standby/wait control. The bit field is only useful when
generic parameter MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read
only register read a 0.
0 Force-standby. Mstandby is forced unconditionally.
1h No-standby. Mstandby is never asserted.
2h Smart-standby modelocal initiator standby status depends on local conditions, i.e. the
module's functional requirement from the initiator.
IP module shall not generate (initiator-related) wake-up events.
3h Smart-Standby wake-up-capable modelocal initiator standby status depends on local
conditions, i.e. the module's functional requirement from the initiator.
IP module can generate (master-related) wake-up events when in standby state. Mode is only
relevant if the appropriate IP module "mwake-up" output is implemented. Functional clock is
maintained. Interface clock may be switched off.
0 These bits are initialized to zero, and writes to them are ignored. Reads return 0.
Clocks activity during wake up mode period.
Bit 8 Interface clock
Bit 9 Functional clock
0 Interface and Functional clock may be switched off.
1h Interface clock is maintained. Functional clock may be switched-off.
2h Functional clock is maintained. Interface clock may be switched-off.
3h Interface and Functional clocks are maintained.
0 These bits are initialized to zero, and writes to them are ignored. Reads return 0.
Power management
0 If an idle request is detected, the SD/SDIO host controller acknowledges it unconditionally and
goes in Inactive mode. Interrupt and DMA requests are unconditionally deasserted.
1h If an idle request is detected, the request is ignored and the module keeps on behaving
normally.
2h If an idle request is detected, the module will switch to wake up mode based on its internal
activity, and the wake up capability can be used if the wake up capability is enabled (bit
SD_SYSCONFIG[2] ENAWAKEUP bit is set to 1).
3h Smart-idle Wake-up capable modelocal target's idle state eventually acknowledges the
system's idle requests, depending on the IP modules internal requirements. IP module may
generate (IRQ- or DMA-request-related) wake-up events when in idle state. Mode is only
relevant if the appropriate IP module "swake-up" output(s) is (are) implemented.
© 2011, Texas Instruments Incorporated
and described in Table
Reserved
R-0
11 10
Reserved
R-0
3 2
ENAWAKEUP
R/W-2h R/W-1
www.ti.com
9-14.
16
9 8
CLOCKACTIVITY
R/W-0
1 0
SOFTRESET AUTOIDLE
R/W-0 R/W-1
SPRUGX9 – 15 April 2011
Submit Documentation Feedback