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11.2.7 Power Management
11.2.7.1 ForceIdle Behavior
When configured in ForceIdle the module should respond immediately (according to the OCP guideline
description) to a McBSP.MIDLEREQ, regardless of the internal state of the module. Entering in this
mode, the module will freeze all the internal activity when the clocks are switched off by the power
management external module. If the functional part, transmit or receive, is running within this period of
time, the internal state of the module will not be idle (FSM states, processes, etc.), and when the
module exits from the ForceIdle state unexpected behavior may happen in both receiver and
transmitter. In order to avoid this both receive and transmit parts need to be disabled by software prior
to MIdleReq assertion.
11.2.7.2 SmartIdle Behavior
When configured in SmartIdle, the sources for wake-up generation are a subset of the interrupt
sources. The wakeup sources are enabled by setting the corresponding bit in WAKEUPEN register.
For receive WAKEUP there are 4 possible configuration scenarios:
•
RRDYEN - The McBSP asserts the McBSP.WAKEUP request when the RB reaches the high
threshold (THRSH1_REG + 1) register value. If the corresponding bit is set in IRQENABLE register,
McBSP sends an interrupt (McBSP.COMMONIRQ) request to the CPU when exiting from idle mode
(interrupt will be asserted once the RRDY bit changes from 0 to 1, indicating that receive data is
ready to be read).
•
REOFEN - The McBSP asserts the McBSP.WAKEUP request at the end of the frame. If the
corresponding bit is set in IRQENABLE register McBSP sends an interrupt (McBSP.COMMONIRQ)
request to the CPU when exit from idle mode.
•
RSYNCERREN - The McBSP asserts the McBSP.WAKEUP request when an unexpected receive
frame-sync pulse is detected. If the corresponding bit is set in IRQENABLE register, McBSP sends
an interrupt (McBSP.COMMONIRQ) request o the CPU when exiting from idle mode (interrupt will
be asserted once the RSYNCERR bit changes from 0 to 1, indicating that a receive error occurred).
For transmit WAKEUP there are four possible configuration scenarios:
•
XRDYEN - The McBSP asserts the McBSP.WAKEUP request when the XB reaches the high
threshold (THRSH2_REG + 1) register value. If the corresponding bit is set in IRQENABLE register,
McBSP sends an interrupt (McBSP.COMMONIRQ) request to the CPU when exiting from idle mode
(interrupt will be asserted once the XRDY bit changes from 0 to 1, indicating that transmit buffer
data is ready to accept new data).
•
XEOFEN - The McBSP asserts the McBSP.WAKEUP request at the end of the frame. If the
corresponding bit is set in IRQENABLE register, the McBSP sends an interrupt
(McBSP.COMMONIRQ) request to the CPU when exiting from idle mode.
•
XFSXEN - The McBSP sends a McBSP.WAKEUP request when a transmit frame-sync pulse is
detected while the module is in idle mode. If the corresponding bit is set in IRQENABLE register, the
McBSP sends an interrupt (McBSP.COMMONIRQ) request to the CPU when exiting from idle mode.
•
XSYNCERREN - The McBSP asserts the McBSP.WAKEUP request when an unexpected transmit
frame-sync pulse is detected. If the corresponding bit is set in IRQENABLE register, the McBSP
sends an interrupt (McBSP.COMMONIRQ) request to the CPU when exiting from idle mode
(interrupt will be asserted once the XSYNCERR bit changes from 0 to 1, indicating that a transmit
error occurred).
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Architecture
1153
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