Table of Contents
Advertisement
www.ti.com
Additionally, the module can be reset by software through the bit SoftReset of the register
MCSPI_SYSCONFIG. This bit has exactly the same action on the module logic as the hardware
RESETN signal. The register MCSPI_SYSCONFIG is not sensitive to software reset. The SoftReset
control bit is active high. The bit is automatically reset to 0 by the hardware.
A global ResetDone status bit is provided in the status register MCSPI_SYSSTATUS. This bit is set to
1 when all the different clock domains resets (OCP domain and SPI domains) have been released
(logical AND).
The global ResetDone status bit can be monitored by the software to check if the module is
ready-to-use following a reset (either hardware or software).
The clock CLKSPIREF must be provided to the module, in order to allow the ResetDone status bit to be
set.
When used in slave mode, the clock CLKSPIREF is needed only during the reset phase. The clock
CLKSPIREF can be switched off after the ResetDone status is set.
12.2.10.2 Reset values of registers
The reset values of registers and signals are described in
12.2.11 Access to Data Registers
This section details the supported data accesses (read or write) from/to the data receiver registers
MCSPI_RX(i) and data transmitter registers MCSPI_TX(i).
Supported access:
McSPI supports only one SPI word per register (receiver or transmitter) and does not support
successive 8-bit or 16-bit accesses for a single SPI word.
The SPI word received is always right justified on LSbit of the 32bit register MCSPI_RX(i), and the SPI
word to transmit is always right justified on LSbit of the 32bit register MCSPI_TX(i).
The upper bits, above SPI word length, are ignored and the content of the data registers is not reset
between the SPI data transfers.
The coherence between the number of bits of the SPI Word, the number of bits of the access and the
enabled byte remains under the user's responsibility. Only aligned accesses are supported.
In Master mode, data should not be written in the transmit register when the channel is disbaled.
12.2.12 Programming Aid
12.2.12.1 Module Initialization
•
Hard or soft reset.
•
Read MCSPI_SYSSTATUS.
•
Check if reset is done.
•
Module configuration: (a) Write into MCSPI_MODULCTRL (b) Write into MCSPI_SYSCONFIG.
•
Before the ResetDone bit is set, the clocks CLK and CLKSPIREF must be provided to the module.
•
To avoid hazardous behavior, it is advised to reset the module before changing from MASTER
mode to SLAVE mode or from SLAVE mode to MASTER mode.
12.2.12.2 Common Transfer Sequence
McSPI module allows the transfer of one or several words, according to different modes:
•
MASTER, MASTER Turbo, MASTER LoSSI, SLAVE
•
TRANSMIT - RECEIVE, TRANSMIT ONLY, RECEIVE ONLY
•
Write and Read requests: Interrupts, DMA
•
SPIEN lines assertion/deassertion: automatic, manual
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Section
© 2011, Texas Instruments Incorporated
12.3.
Multichannel Serial Port Interface (McSPI)
Architecture
1249
Advertisement
Table of Contents
