Usbss Irq_Dma_Threshold_Tx0_1 Register (Irqdmatholdtx01); Usbss Irq_Dma_Threshold_Tx0_2 Register (Irqdmatholdtx02); Usbss Irq_Dma_Threshold_Tx0_1 Register (Irqdmatholdtx01) Field Descriptions; Usbss Irq_Dma_Threshold_Tx0_2 Register (Irqdmatholdtx02) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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20.9.1.9 USBSS IRQ_DMA_THRESHOLD_TX0_1 Register (IRQDMATHOLDTX01)

The USBSS IRQ_DMA_THRESHOLD_TX0_1 register (IRQDMATHOLDTX01) defines the size of the
four DMA thresholds for interrupt pacing for USB0. Each threshold contains an 8-bit unsigned number
and can range from 0 to 255. A possible interrupt can be triggered if the count for that specific endpoint
has exceeded the value of the threshold. The counter for the compared value is also an 8-bit unsigned
number; therefore, setting the threshold to 255 prevents the possibility of a trigger.
The USBSS IRQ_DMA_THRESHOLD_TX0_1 register is shown in
Table 20-40.
Figure 20-30. USBSS IRQ_DMA_THRESHOLD_TX0_1 Register (IRQDMATHOLDTX01)
31
dma_thres_tx0_7
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-40. USBSS IRQ_DMA_THRESHOLD_TX0_1 Register (IRQDMATHOLDTX01) Field
Bits Field
31-24 dma_thres_tx0_7
23-16 dma_thres_tx0_6
15-8 dma_thres_tx0_5
7-0 dma_thres_tx0_4

20.9.1.10 USBSS IRQ_DMA_THRESHOLD_TX0_2 Register (IRQDMATHOLDTX02)

The USBSS IRQ_DMA_THRESHOLD_TX0_2 register (IRQDMATHOLDTX02) defines the size of the
four DMA thresholds for interrupt pacing for USB0. Each threshold contains an 8-bit unsigned number
and can range from 0 to 255. A possible interrupt can be triggered if the count for that specific endpoint
has exceeded the value of the threshold. The counter for the compared value is also an 8-bit unsigned
number; therefore, setting the threshold to 255 prevents the possibility of a trigger.
The USBSS IRQ_DMA_THRESHOLD_TX0_2 register is shown in
Table 20-41.
Figure 20-31. USBSS IRQ_DMA_THRESHOLD_TX0_2 Register (IRQDMATHOLDTX02)
31
dma_thres_tx0_11
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-41. USBSS IRQ_DMA_THRESHOLD_TX0_2 Register (IRQDMATHOLDTX02) Field
Bits Field
31-24 dma_thres_tx0_11
23-16 dma_thres_tx0_10
15-8 dma_thres_tx0_9
7-0 dma_thres_tx0_8
SPRUGX9 – 15 April 2011
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24 23
dma_thres_tx0_6
R/W-0
Description
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 7.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 6.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 5.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 4.
24 23
dma_thres_tx0_10
R/W-0
Description
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 11.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 10.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 9.
DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 8.
© 2011, Texas Instruments Incorporated
Preliminary
Figure 20-30
16 15
dma_thres_tx0_5
R/W-0
Descriptions
Figure 20-31
16 15
dma_thres_tx0_9
R/W-0
Descriptions
Registers
and described in
8 7
dma_thres_tx0_4
R/W-0
and described in
8 7
dma_thres_tx0_8
R/W-0
Universal Serial Bus (USB)
0
0
1837