Table of Contents
Advertisement
www.ti.com
The following sample code shows the previous steps:
The following code is an assembly code compatible with ARM architecture
V6 and V7. This code is developed for the Texas Instruments Code
Composer Studio tool set. It is a draft version, only tested on an emulated
environment.
; bit field mask to get only the bit field
ACTIVEPRIO_MASK .equ 0x7F
_IRQ_ISR:
; Step 1 : Save the critical context
STMFD SP!, {R0-R12, LR} ; Save working registers
MRS R11, SPSR ; Save the SPSR into R11
; Step 2 : Save the INTCPS_THRESHOLD register into R12
LDR R0, INTCPS_THRESHOLD_ADDR
LDR R12, [R0]
(1) The priority-threshold mechanism is enabled automatically when writing a priority in the
range of 0x00 to 0x7F. Writing a value of 0xFF (reset default) disables the priority-threshold
mechanism. Values between 0x3F and 0xFF must not be used. When the hardware-priority threshold
is in use, the priorities of interrupts selected as FIQ or IRQ become linked otherwise, they
are independent. When they are linked, all FIQ priorities must be set higher than all IRQ
priorities to maintain the relative priority of FIQ over IRQ.
(2) When handling FIQs using the priority-threshold mechanism, both NEWFIQAGR and NEWIRQAGR
bits must be written at the same time to ensure that the new priority threshold is applied
while an IRQ sort is in progress. This IRQ will not have been seen by the ARM, as it will have
been masked on entry to the FIQ ISR. However, the source of the IRQ remains active and it is
finally processed when the priority threshold falls to a priority sufficiently low to allow it
to be processed. The precaution of writing to New FIQ Agreement is not required during an IRQ
ISR, as FIQ sorting is not affected (provided all FIQ priorities are higher than all IRQ
priorities).
; Step 3 : Get the priority of the highest priority active IRQ
LDR R1, INTCPS_IRQ_PRIORITY_ADDR/INTCPS_FIQ_PRIORITY_ADDR
LDR R1, [R1] ; Get the INTCPS_IRQ_PRIORITY/INTCPS_FIQ_PRIORITY register
AND R1, R1, #ACTIVEPRIO_MASK ; Apply the mask to get the priority of the IRQ
STR R1, [R0] ; Write it to the INTCPS_THRESHOLD register
; Step 4 : Get the number of the highest priority active IRQ
LDR R10, INTCPS_SIR_IRQ_ADDR/INTCPS_SIR_FIQ_ADDR
LDR R10, [R10] ; Get the INTCPS_SIR_IRQ/INTCPS_SIR_FIQ register
AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number
; Step 5 : Allow new IRQs and FIQs at INTC side
MOV R0, #0x1/0x3 ; Get the NEWIRQAGR and NEWFIQAGR bit position
LDR R1, INTCPS_CONTROL_ADDR
STR R0, [R1] ; Write the NEWIRQAGR and NEWFIQAGR bit
; Step 6 : Data Synchronization Barrier
MOV R0, #0 MCR P15, #0, R0, C7, C10, #4
; Step 7 : Read-modify-write the CPSR to enable IRQs/FIQs at ARM side
MRS R0, CPSR ; Read the status register
BIC R0, R0, #0x80/0x40 ; Clear the I/F bit
MSR CPSR, R0 ; Write it back to enable IRQs
; Step 8 : Jump to relevant subroutine handler
LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8
NOP ; To index the table by the PC
; Table of handler start addresses
.word IRQ0handler ;IRQ0 BANK0
.word IRQ1handler
.word IRQ2handler
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
CAUTION
© 2011, Texas Instruments Incorporated
Basic Programming Model
913
Interrupt Controller
Advertisement
Table of Contents
