Secstat Register; Secstat Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

13.4.7.5 SECSTAT Register

The secondary status and IO base/limit register (SECSTAT) is described in the figure and table below.
31 30
DTCT_PERROR RX_SYS_ERROR RX_MST_ABORT RX_TGT_ABORT
R/W1C-0 R/W1C-0
23
15
IO Limit
7
IO Base
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Bit Field
31 DTCT_PERROR
30 RX_SYS_ERROR
29 RX_MST_ABORT
28 RX_TGT_ABORT
27 TX_TGT_ABORT
26-25 Reserved
24 MST_DPERR
23-16 Reserved
15-12 IO Limit
11-9 Reserved
8 IO Addressing
7-4 IO Base
3-1 Reserved
0 IO Addressing
1358
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-96. SECSTAT Register
29 28
R/W1C-0 R/W1C-0
12
R/W-0
4
R/W-0
Table 13-102. SECSTAT Register Field Descriptions
Value Description
0 Detected Parity Error
0 Received System Error
0 Received Master Abort
0 Received Target Abort
0 Signaled Target Abort
0 Reserved
0 Master Data Parity Error
0 Reserved
0-Fh I/O Space Limit
0 Reserved
0 32 bit IO Space indication for IO Limit Register. Indicates 16 bit and 32 bit addressing for 0 and 1
respectively.
0-Fh IO Space Base
0 Reserved
0 Indicates 0 for 16 bit and 1 for 32 bit addressing for the IO Base Register. Writable from internal
bus interface.
© 2011, Texas Instruments Incorporated
27 26
TX_TGT_ABORT
R/W1C-0
Reserved
R-0
11
Reserved
R-0
3
Reserved
R-0
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25 24
Reserved MST_DPERR
R-0 R/W1C-0
16
9 8
IO Addressing
R-0
1 0
IO Addressing
R-0
SPRUGX9 – 15 April 2011
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