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Basic Programming Model
8.3.3 INTC Preemptive Processing Sequence
Preemptive interrupts, also called nested interrupts, can reduce the latencies for higher priority
interrupts. A preemptive ISR can be suspended by a higher priority interrupt. Thus, the higher priority
interrupt can be served immediately. Nested interrupts must be used carefully to avoid using corrupted
data. Programmers must save corruptible registers and enable IRQ or FIQ at ARM side. IRQ and FIQ
processing sequences are quite similar, the differences for the FIQ sequence are shown after a '/'
character in the code below.
To enable IRQ/FIQ preemption by higher priority IRQs/FIQs, programers can follow this procedure to
write the ISR.
At the beginning of an IRQ/FIQ ISR:
1. Save the ARM critical context registers.
2. Save the INTCPS_THRESHOLD PRIORITYTHRESHOLD field before modifying it.
3. Read the active interrupt priority in the INTCPS_IRQ_PRIORITY
IRQPRIORITY/INTCPS_FIQ_PRIORITY FIQPRIORITY field and write it to the
PRIORITYTHRESHOLD(1) field.
4. Read the active interrupt number in the INTCPS_SIR_IRQ[6:0] ACTIVEIRQ/INTCPS_SIR_FIQ[6:0]
ACTIVEFIQ field to identify the interrupt source.
5. Write 1 to the appropriate INTCPS_CONTROL NEWIRQAGR and (2) NEWFIQAGR bit while an
interrupt is still processing to allow only higher priority interrupts to preempt.
6. Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done
before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the
IRQ line is de-asserted before IRQ/FIQ enabling.
7. Enable IRQ/FIQ at ARM side.
8. Jump to the relevant subroutine handler.
912
Interrupt Controller
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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