Table of Contents
Advertisement
Registers
Table 7-8. I2C Status Raw Register (I2C_IRQSTATUS_RAW) Field Descriptions (continued)
Bit
Field
Value
9
AAS
0
1
8
BF
0
1
7
AERR
0
1
6
STC
0
1
864
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Description
Address recognized as slave IRQ status. I2C mode only.
This read only bit is set to 1 by the device when it has recognized its own slave address (or one of the
alternative own addresses), or an address of all zeros (8 bits). When this bit is set to 1 by the core, an
interrupt is signaled to the local host if the interrupt was enabled.
This bit can be cleared in 2 ways:
• If the interrupt was enabled, it will be cleared by writing 1 into this register (writing 0 has no effect)
• If the interrupt was not enabled, the AAS bit is reset to 0 by restart or stop
No action
Address recognized
Value after reset is low.
I2C mode only.
This read only bit is set to 1 by the device when the I2C bus became free (after a transfer is ended on
the bus – stop condition detected). This interrupt informs the Local Host that it can initiate its own I2C
transfer on the bus.
When this bit is set to 1 by the core, an interrupt is signaled to the local host if the interrupt was
enabled. The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no effect.
No action
Bus Free
Value after reset is low.
Access Error IRQ status. I2C mode only.
This read/clear only bit is set to 1 by the device if an OCP write access is performed to I2C_DATA
while the TX FIFO is full or if an OCP read access is performed to the I2C_DATA while the RX FIFO is
empty.
Note that, when the RX FIFO is empty, a read access will return to the previous read data value. When
the TX FIFO is full, a write access is ignored. In both events, the FIFO pointers will not be updated.
When this bit is set to 1 by the core, an interrupt is signaled to the local host if the interrupt was
enabled. The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no effect.
No action
Access Error
Value after reset is low.
Start Condition IRQ status. I2C mode only.
This read/clear only bit is set to 1 by the device if previously the module was in idle mode and a start
condition was asynchronously detected on the I2C Bus and signalized with an Wakeup (if the
I2C_SYSC.ClockActivity allows the system clock to be cut-off). When the Active Mode will be restored
and the interrupt generated, this bit will indicate the reason of the wakeup.
Note 1: The corresponding interrupt for this bit should be enabled only if the module was configured to
allow the possibility of cutting-off the system clock while in Idle State (I2C_SYSC.ClockActivity = 00 or
01).
Note 2: The first transfer (corresponding to the detected start condition) will be lost (not taken into
account by the module) and it will be used only for generating the WakeUp enable for restoring the
Active Mode of the module. On the I2C line, the external master which generated the transfer will
detect this behavior as a not acknowledge to the address phase and will possibly restart the transfer.
The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no effect.
No action
Start Condition detected
Value after reset is low.
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
