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Table 9-32. Interrupt Status Register (SD_STAT) Field Descriptions (continued)
Bit
Field
8
CIRQ
7
CREM
6
CINS
5
BRR
4
BWR
3
DMA
SPRUGX9 – 15 April 2011
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Preliminary
Value
Description
Card interrupt. This bit is only used for SD and SDIO cards.
In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wake-up).
In 4-bit mode, interrupt source is sampled during the interrupt cycle.
In CE-ATA mode, interrupt source is detected when the card drives SD_CMD line to zero
during one cycle after data transmission end.
All modes above are fully exclusive.
The controller interrupt must be clear by setting SD_IE[8] CIRQ_ENABLE to 0, then the host
driver must start the interrupt service with card (clearing card interrupt status) to remove card
interrupt source. Otherwise the Controller interrupt will be reasserted as soon as SD_IE[8]
CIRQ_ENABLE is set to 1.
Writes to this bit are ignored.
Read 0
No card interrupt
Read 1
Generate card interrupt
Card Removal. This bit is set automatically when SD_PSTATE[CINS] changes from 1 to 0. A
clear of this bit doesn't affect Card inserted present state (SD_PSTATE[CINS]).
Read 0
Card State stable or debouncing
Write 0
Status bit unchanged
Read 1
Card Removed
Write 1
Status is cleared
Card Insertion. This bit is set automatically when SD_PSTATE[CINS] changes from 0 to 1. A
clear of this bit doesn't affect Card inserted present state (SD_PSTATE[CINS]).
Read 0
Card State stable or debouncing
Write 0
Status bit unchanged
Read 1
Card inserted
Write 1
Status is cleared.
Buffer read ready. This bit is set automatically during a read operation to the card (see class 2
- block oriented read commands) when one block specified by the SD_BLK[10:0] BLEN bit
field is completely written in the buffer. It indicates that the memory card has filled out the
buffer and that the local host needs to empty the buffer by reading it.
NoteIf the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request
to the main DMA controller of the system is generated.
Read 0
Not ready to read buffer
Write 0
Status bit unchanged
Read 1
Ready to read buffer
Write 1
Status is cleared.
Buffer write ready. This bit is set automatically during a write operation to the card (see class 4
- block oriented write command) when the host can write a complete block as specified by
SD_BLK[10:0] BLEN. It indicates that the memory card has emptied one block from the buffer
and that the local host is able to write one block of data into the buffer.
NoteIf the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit
request to the main DMA controller of the system is generated.
Read 0
Not ready to write buffer
Write 0
Status bit unchanged
Read 1
Ready to write buffer
Write 1
Status is cleared.
DMA Interrupt. This status is set when an interrupt is required in the ADMA instruction and
after the data transfer completion.
Read 0
DMA Interrupt detected
Write 0
Status bit unchanged
Read 1
No DMA Interrupt
Write 1
Status is cleared.
© 2011, Texas Instruments Incorporated
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Registers
993
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