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Communications Port Programming Interface (CPPI) 4.1 DMA
20.4.9.1.3 USB 2.0 Core Transmits USB Packets for Tx (Step 3)
1. Once the XDMA has transferred enough 64-byte blocks of burst of data from the CPPI FIFO to fill
the Endpoint FIFO (accumulated 512 bytes), it signals the Mentor USB 2.0 Core that a TX packet is
ready (sets the endpoint's TxPktRdy bit).
2. The USB 2.0 Core will transmit the packet from the Endpoint FIFO out on the USB BUS when it
receives a corresponding IN request from the attached USB Host.
3. After the USB packet is transferred, the USB 2.0 Core issues a TX DMA_req to the XDMA.
4. This process is repeated until (the above steps '1', '2', and '3') the entire packet has been
transmitted. The XDMA will also generate the required termination packet depending on the
termination mode configured for the endpoint.
20.4.9.1.4 Return Packet to Completion Queue and Interrupt CPU for Tx (Step 4)
1. After all data for the packet has been transmitted (as specified by the packet size field), the CDMA
will write the pointer of the Packet Descriptor only to the TX Completion Queue specified in the
return queue manager / queue number fields of the packet descriptor.
2. The Queue Manager then indicates the status of the TXSQ (empty) to the CDMAS and the TXCQ to
the CPU via an interrupt.
20.4.9.2 Receive USB Data Flow Using DMA
The receive buffer descriptors and queue status configuration prior to the transfer taking place is shown
in
Figure
20-19.
20.4.9.2.1 Receive Initialization (Step 1)
1. The CPU initializes Queue Manager with the Memory Region 0 base address and Memory Region 0
size, Link RAM0 Base address, Link RAM0 data size, and Link RAM1 Base address.
2. The CPU creates BDs, and DBs in main memory and link them creating a BD and DB pairs.
3. CPU then initializes the RXCQ queue and configures the Queue Manager, Channel Setup, DMA
Scheduler, and USB 2.0 Core.
4. It then adds (pushes) the address of the addresses/pointers of three Buffer Descriptors (PBDs) into
the RXSQ by writing onto CTRL D register.
Figure 20-20
displays receive operation Initialization.
20.4.9.2.2 USB 2.0 Core Receives a Packet, XDMA Starts Data Transfer for Receive (Step 2)
1. The USB 2.0 Core receives a USB packet from the USB Host and stores it in the Endpoint FIFO.
2. It then asserts a DMA_req to the XDMA informing it that data is available in the Endpoint FIFO.
3. The XDMA verifies the corresponding CPPI FIFO is not full via the FIFO_full signal, then starts
transferring 64-byte data blocks (burst) from the Endpoint FIFO into the CPPI FIFO.
1816
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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