Cm_Timer6_Clksel Register; Cm_Sysclk23_Clksel Register; Cm_Timer6_Clksel Register Field Descriptions; Cm_Sysclk23_Clksel Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

14.7.4.30 CM_TIMER6_CLKSEL Register

The CM_TIMER6_CLKSEL register selects the Mux select line for TIMER6 clock. It is shown and
described in the figure and table below
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-2 Reserved
1-0 CLKSEL

14.7.4.31 CM_SYSCLK23_CLKSEL Register

The CM_SYSCLK23_CLKSEL register selects the divider value for SYSCLK23. It is shown and
described in the figure and table below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-63. CM_SYSCLK23_CLKSEL Register Field Descriptions
Bit Field
31-3 Reserved
2-0 CLKSEL
1446
Power, Reset, and Clock Management (PRCM) Module
Preliminary
Figure 14-47. CM_TIMER6_CLKSEL Register
Reserved
R-0
Table 14-62. CM_TIMER6_CLKSEL Register Field Descriptions
Value Description
0 Reserved
Selects the Mux select line for TIMER6 clock [warm reset insensitive]
0 Select TIMER clock to be TCLKIN
1h Select TIMER clock to be external 32 KHz clock.(After MUX)
2h Select TIMER clock to be CLKIN
3h Reserved
Figure 14-48. CM_SYSCLK23_CLKSEL Register
Reserved
R-0
Value Description
0 Reserved
Selects the divider value [warm reset insensitive]
0 Select SYS_CLK divided by 1
1h Select SYS_CLK divided by 2
2h Select SYS_CLK divided by 3
3h Select SYS_CLK divided by 4
4h Select SYS_CLK divided by 5
5h Select SYS_CLK divided by 6
6h Select SYS_CLK divided by 7
7h Select SYS_CLK divided by 8
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2 1 0
CLKSEL
R/W-1
3 2 0
CLKSEL
R/W-0
SPRUGX9 – 15 April 2011
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