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Architecture
11.2.3 McBSP Exception/Error Conditions
There are several serial port events that can constitute a system error. Any of this error conditions may
be sources of an interrupt:
•
Receiver Overrun
(ROVFLSTAT bit is set to 1 in IRQSTATUS register, and legacy mode RFULL bit is set to 1 in
SPCR1_REG register)
This occurs when receive buffer is full and RSR(s) are full with another new word shifted in from
McBSP.DR. Therefore, ROVFLSTAT (RFULL) indicates an error condition wherein any new data that
can arrive at this time on McBSP.DR replaces the contents of the RSR, and the previous word is lost.
The RSR continue to be overwritten as long as new data arrives on McBSP.DR and DRR_REG register
is not read.
•
Unexpected Receive Frame-Synchronization Pulse
(RSYNCERR bit is set to 1 in IRQSTATUS register, and legacy mode RSYNCERR bit is set to 1 in
SPCR1_REG register)
This occurs during reception when an unexpected frame–synchronization pulse arrives. An unexpected
frame-synchronization pulse is one that is supposed to begin the next frame transfer before all the bits
of the current frame have been received. Such a pulse is ignored by the receiver, but sets the
RSYNCERR bit in SPCR1_REG.
•
Receiver Underflow
(RUNDFLSTAT bit is set to 1 in IRQSTATUS register)
This occurs when DMA controller or CPU reads data from an empty receive buffer.
•
Transmitter Underflow
(XUNDFLSTAT bit is set to 1 in IRQSTATUS register, and legacy mode XEMPTY bit is cleared to 0 in
SPCR2_REG register)
If a new frame–synchronization signal arrives when transmit buffer is empty, the previous data in the
XSR is sent again. This procedure continues for every new frame–synchronization pulse that arrives
until DXR_REG register is loaded with new data (and the XB buffer will be no longer empty).
•
Unexpected Transmit Frame-Synchronization Pulse
(XSYNCERR bit is set to 1 in IRQSTATUS register, and legacy mode XSYNCERR bit is set to 1 in
SPCR2_REG register)
This occurs during transmission when an unexpected frame–synchronization pulse arrives. An
unexpected frame–synchronization pulse is one that is supposed to begin the next frame transfer
before all the bits of the current frame have been transferred. Such a pulse is ignored by the
transmitter, but sets the XSYNCERR bit in SPCR2_REG.
•
Transmitter Overflow
(XOVFLSTAT bit is set to 1 in IRQSTATUS register)
This occurs when DMA controller or CPU write data to a full transmit buffer.
1138
Multichannel Buffered Serial Port (McBSP)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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