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For more details about how MSI interrupts are expected to behave, refer to PCIe Standard
Specifications.
13.2.9.3 Interrupt Reception
Since the PCIESS is capable of assuming a role of RC or EP, interrupt reception capability is
dependant upon the role it is assuming.
13.2.9.3.1 Interrupt Reception in EP Mode
The PCIe specification does not have provision for End Points to receive legacy interrupts. As a result,
only events other than PCIe related can cause interrupts. The MSI interrupts are not supported on EP
devices as per PCIe Specification but PCIESS does support these interrupts. The MSI interrupt is
generated as a result of the one of 32 events that are trigger by a write to MSI_IRQ register by the RC.
These interrupts, delivered via register writes over the serial link, could also be coming from another
End Point that performs a write to the appropriate interrupt registers in the EP's BAR0 space. It is up to
software designers to implement a way to determine the actual source of the interrupt.
13.2.9.3.1.1 Host Reset Request Interrupt Reception in EP Mode
When the link is down, the upstream port may request reset of the End Point. This request is
terminated as an interrupt to the End Point host software. The PCIESS automatically disables LTTSSM
by de-asserting app_ltssm_enable bit in CMD_STATUS register and suspends LTSSM in DETECT
QUIET state. All outstanding transactions are errored out on slave port and further transactions are no
generated on master port. Once the transactions are completely stopped through OCP disconnect
protocol, the software should issue a local reset to PCIESS. The re-initialization process may then be
started.
13.2.9.3.2 Interrupt Reception in RC Mode
When PCIESS operates in RC Mode the Endpoints on the PCI fabric can be a Switch, PCIe EP or
Legacy EP. For this reason, it should be able to handle both MSI and Legacy Interrupt.
13.2.9.3.2.1 MSI Interrupt Reception in RC Mode
A total of 32 MSI interrupts can be generated from one or more downstream devices. These MSI
interrupts represent the MSI interrupts that have been allocated to various downstream devices during
PCIe configuration/enumeration procedure. Before the End Point devices can issue MSI interrupts, the
MSI address and data registers must be configured. Each End Point can either use MSI interrupts or
legacy interrupts and not both at the same time. MSI interrupt have the same race condition hazard as
the legacy interrupts. Hence, software drivers should take precaution.
13.2.9.3.2.2 Legacy Interrupt Reception in RC Mode
Any of the four legacy interrupts may be generated by the PCIESS. Each interrupt can originate from
multiple End Point devices. The software should service these by probing the interrupt registers in each
downstream device's configuration space. When all devices have been serviced, the last device
serviced will send a interrupt deassert message which will clear the interrupt.
The interrupt request signal at the PCIESS boundary is a pulse signal that is triggered each time a
assert interrupt message is received. The interrupt pending signal is a level signal that is high as long
as the interrupt has not be serviced and the interrupt status not cleared through a register write.
Note that the traditional EOI procedure, although implemented, may not operate as expected if the
deassert message arrives after the EOI has been issued. This can not be corrected but only worked
around by doing a read on the interrupt register downstream before issuing EOI. If the EOI register is
written to before the deassert message has reached the interrupt logic, the interrupt pending status will
not have cleared and the interrupt will re-trigger.
SPRUGX9 – 15 April 2011
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Preliminary
Peripheral Component Interconnect Express (PCIe)
© 2011, Texas Instruments Incorporated
Architecture
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