Receive Clock Generator Block Diagram - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
10.2.2.2 Receive Clock
The receiver also has the option to operate synchronously from the ACLKX and AFSX signals. This is
achieved when the ASYNC bit in the transmit clock control register (ACLKXCTL) is cleared to 0 (see
Figure 10-17). The receiver may be configured with different polarity (CLKRP) and frame sync data
delay options from those options of the transmitter.
The receive clock configuration is controlled by the following registers:
• ACLKRCTL.
• AHCLKRCTL.
AHCLKR
pin
(internal/external)
(AHCLKRCTL.15)
ACLKR
pin
(internal/external)
1026
Multichannel Audio Serial Port (McASP)
Preliminary
Figure 10-17. Receive Clock Generator Block Diagram
1
0
HCLKRM
1
0
CLKRM
(ACLKRCTL.5)
CLKRP
(polarity)
(ACLKRCTL.7)
© 2011, Texas Instruments Incorporated
Divider
/1... /4096
HCLKRDIV
(AHCLKRCTL[11−0])
Divider
0
/1... /32
CLKRDIV
1
(ACLKRCTL[4−0])
HCLKRP
(polarity)
(AHCLKRCTL.14)
1
1
0 RCLK
0
ASYNC
(ACLKXCTL.6)
XCLK
(from Figure 16)
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AUXCLK
SPRUGX9 – 15 April 2011
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