Related Manuals for Texas Instruments TMS320TCI648 Series
Summary of Contents for Texas Instruments TMS320TCI648 Series
- Page 1 TMS320TCI648x/9x DSP Viterbi-Decoder Coprocessor 2 (VCP2) User's Guide Literature Number: SPRUE09E May 2006 – Revised December 2009...
- Page 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
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Page 3: Table Of Contents
....................11.2 VCPREVT Generation ......................Operational Modes ....................12.1 Debugging Features ......................Errors and Status ...................... Appendix A Revision History SPRUE09E – May 2006 – Revised December 2009 Table of Contents Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... - Page 4 ............Mixed Traceback Mode-Example With Five Sliding Windows ..........Convergent Traceback Mode-Example With Five Sliding Windows ................... EDMA3 Parameters Structure List of Figures SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
- Page 5 Traceback Hard Decision Sliding Window Limits ....................Code Rate versus SYMX ................Required EDMA3 Links Per User Channel ..................... TCI648x/9x Revision History SPRUE09E – May 2006 – Revised December 2009 List of Tables Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
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Page 6: Preface
The VCP2 coprocessor offers a very cost effective and synergistic solution when combined with Texas Instruments (TI) DSPs. The VCP2 supports 762 12.2 Kbps 3G AMR channels when running at 333 MHz. This document describes the operation and programming of the VCP2. -
Page 7: Features
– Uses its own optimized working memories – Provides debug capabilities during frame processing – Libraries are provided for reduced development time SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 8: Introduction
Once a path through the trellis is identified, the traceback routine performs a backward recursion in the trellis and outputs hard decisions or soft decisions. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 9: Trellis Diagram For Convolutional Encoder Example
0/000 means input is 0, output1 is (K-1) 0, output2 is 0, output3 is 0. There are 2 states and 2 incoming branches per state. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 10: Overview
VCPXEVT VCPREVT REVT/XEVT interrupt generation generation VCP Control EDMA3 I/F unit Memory block Processing unit Viterbi-decoder coprocessor 2 (VCP2) TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 11: Input Data
Table 1. Branch Metrics for Rate 1/2 Data Address (hex) Base (t=T) (t=T) (t=0) (t=0) Base + 4h (t=3T) (t=3T) (t=2T) (t=2T) Base + 8h SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 12: Soft Input Dynamic Ranges
5, 6, 7, 8, 9 [-64; +63] 5, 6, 7, 8, 9 0.333333 [-42; +42] 5, 6, 7, 8, 9 0.25 [-31; +31] TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 13: Decision Data
The soft decisions in the VCP2 are initially computed with the path metrics at 13-bit values. The results are then clipped to 8-bit signed integer values before being stored in the traceback soft decision memory. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 14: Registers
8-byte (double-word) multiple. • Emulation mode transfers are performed on 32-bit boundaries and are 4 bytes in length. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 15: Vcp2 Peripheral Identification Register (Vcppid)
RTL revision code. 10-8 MAJOR <major> Major revision code. CUSTOM <custom> Custom revision code. MINOR <minor> Minor revision code. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 16: Vcp2 Input Configuration Register 0 (Vcpic0)
POLYn fields not used by the current code rate must be set to zero. The VCP2 uses the number of least-significant bits that are zero in POLY0 to determine the constraint length. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 17: Vcp2 Input Configuration Register 1 (Vcpic1)
15-0 Reserved Reserved. These reserved bit locations must be 0. A value written to this field has no effect. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 18: Vcp2 Input Configuration Register 2 (Vcpic2)
TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 19: Vcp2 Input Configuration Register 3 (Vcpic3)
> F + (K-1) in mixed mode, or if f > F + C in convergence mode (see Section 8.1.4). SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 20: Vcp2 Input Configuration Register 4 (Vcpic4)
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. 12-0 IMAXS 0-1FFFh Maximum initial state metric (13 bits). TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 21: Vcp2 Input Configuration Register 5 (Vcpic5)
(IMAXS) bits in VCPIC4; all the other states are initialized with the value in the IMINS bits. For more details on F , see Section 8.1.4. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 22: Vcp2 Output Register 0 (Vcpout0)
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. 12-0 FMAXS 0-FFFh Maximum state metric value for the final trellis stage (at trellis stage R+C). 13 bits TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 23: Vcp2 Output Register 1 (Vcpout1)
0-FFFh State index for the state with the final maximum state metric. There are 2 state metrics for each (k-1) trellis stage. Valid range for FMAXI is 0 to 2 SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 24: Vcp2 Execution Register (Vcpexe)
Stop. Soft reset all VCP registers to their initial condition. All registers in the VCP are reset in this mode except for the execution register, endian register, emulation register, and other internal registers. 6h-FFh Reserved TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 25: Vcp2 Endian Mode Register (Vcpend)
Traceback soft-decision memory format select bit. 32-bit-word packed. Native format (8 bits). Branch metrics memory format select bit. 32-bit-word packed. Native format (8 bits). SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 26: Vcp2 Status Register 0 (Vcpstat0)
FIFO buffer is becoming empty or if the output FIFO buffer is full. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 27: Vcp2 Status Register 1 (Vcpstat1)
Number of symbols in the output FIFO buffer. 15-0 NSYMIF 0-FFFFh Number of symbols in the input FIFO buffer. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 28: Vcp2 Error Register (Vcperr)
Traceback mode is not allowed. (1 to 3 are valid modes) For more details on F , see Section 8.1.4. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... - Page 29 Table 20. VCP2 Error Register (VCPERR) Field Descriptions (continued) Field Value Description ERROR No error is detected. An error has occurred SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
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Page 30: Vcp2 Emulation Control Register (Vcpemu)
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. FREE Free bit Reserved Free run mode - vcp_emususp signal and functions normally. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 31: Endianness
Figure 20. Data Destination - Kernel for Processing Unit (BM = 1) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 32: Data Source - Vbusp/Dma (Bm = 0)
Figure 22. Data Destination - Kernel for Processing Unit (BM = 0) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 33: Trellis Stage Ordering Of Hard Decisions In 32-Bit Word (Out_Order = 0)
7,6,5,4,3,2,1,0 Þ 0, 1, 2, 3, 4, 5, 6, 7 (bytes) Endianness manager has no effect 7,6,5,4,3,2,1,0 Þ 7,6,5,4,3,2,1,0 (bytes) Endianness manager has no effect 7,6,5,4,3,2,1,0 Þ 7,6,5,4,3,2,1,0 (bytes) SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 34: Architecture
They are output in reverse order and in blocks of user-defined size. Figure 26. Tailed Traceback Mode SM computation K−1 TB computation Only output F decisions TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 35: Mixed Traceback Mode-Example With Five Sliding Windows
SW : R+C symbols R’ K−1 Last SW : R’+K−1 symbols SM computation TB computation Only output R decisions SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 36: Traceback Soft Decision Sliding Window Limits
The maximum value for the FL input parameter is F for tailed mode or (r+c) for mixed or convergent modes. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 37: Yamamoto Parameters
– If F ≤ 2048, then SYMR = ceil (F/64) - 1 – If F > 2048, then SYMR = 15 or 31 • For soft decisions: SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... - Page 38 F ≤ 256, for soft decision output, and SYMR is calculated as shown, a single VCPREVT event is generated once all the output data has been written to the output FIFO. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
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Page 39: Programming
BCNTRLD LINK Destination 3rd Dimension Index (DSTCIDX) Source 3rd Dimension Index (SRCCIDX) Reserved Number of frames in block (CCNT) SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 40: Branch Metrics
(r - 1) For mixed and tailed traceback mode, Total number of Branch Metrics = (F + K - 1) ×(2 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... - Page 41 (Framelength/8). • Destination Address: hard-decision array address • SRCBIDX = 0 • DSTBIDX = ACNT • SRCCIDX = 0 SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
- Page 42 BCNT = 1 • Destination Address: output register store array address • SRCBIDX = 0 • DSTBIDX = 0 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated...
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Page 43: Input Configuration Words
The FMAXI bit in VCPOUT1 indicates the state index for the state with the final maximum state metric. The YAM bit in VCPOUT1 is described in Section 8.2. SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 44: Event Generation
After the traceback is completed (the whole frame has been decoded). • OUTF bit in VCPIC5 is 1 and all decisions have been read to read the output registers. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 45: Operational Modes
SPRUE09E – May 2006 – Revised December 2009 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 46: Errors And Status
In such cases, a watchdog timer should be used and set according to the frame length and VCP2 configuration, in addition to some overhead to allow for EDMA3 usage. TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... -
Page 47: Appendix A Revision History
Table 30. TCI648x/9x Revision History Additions/Modifications/Deletions Table 10 Modified bits 15-0, FL, description Section 8.1.4 Modified step 4 in numbered list Modified last paragraph SPRUE09E – May 2006 – Revised December 2009 Revision History Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated... - Page 48 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.