Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1578

C6-integra dsp+arm processors
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Use Cases
}CommandTable;
//-----------Command Table Data Structure end ---
/////////////////////////////////////////////////////////////////////////////////////////////
// Receive FIS requires the Receive FIS to be 256 byte aligned. P0FB should be programmed
//
with this restriction.
//
// RECEIVE FIS Data Structure
// Members: DMA Setup FIS (DSFIS)
//
PIO Setup FIS (PSFIS)
//
D2H Register FIS (RFIS)
//
Set Device Bits FIS (SDBFIS)
//
Unknown FIS (UFIS)
//-----------DMA Setup FIS-----------------------
typedef struct {
Uint32 B0FisType:8;//bits[7:0]
Uint32 BYTE1:8;
Uint32 B2Rsv:8;
Uint32 B3Rsv:8;
}DsfisW0;
typedef struct {
DsfisW0 DW0;
Uint32 DW1DmaBuffLow;
Uint32 DW2DmaBuffHigh;
Uint32 DW3Rsv;
Uint32 DW4DmaBuffOffset;
Uint32 DW5DmaXfrCnt;
Uint32 DW6Rsv;
}DMASetupFis;
//-----------DMA Setup FIS end PIO Setup FIS ----
typedef struct {
Uint32 B0FisType:8;//bits[7:0]
Uint32 BYTE1:8;
Uint32 B2Status:8;
Uint32 B3Errror:8;//bits[31:24]
}PioSetupDW0;
typedef struct {
Uint32 B0LbaLow:8; //bits[7:0]
Uint32 B1LbaMid:8; //bits[15:8]
Uint32 B2LbaHigh:8;//bits[23:16]
Uint32 B3Device:8; //bits[31:24]
}PioSetupDW1;
typedef struct {
Uint32 B0LbaLowExp:8; //bits[7:0]
Uint32 B1LbaMidExp:8; //bits[15:8]
Uint32 B2LbaHighExp:8;//bits[23:16]
Uint32 B3Rsv:8;
}PioSetupDW2;
typedef struct {
Uint32 B0SecCnt:8;
Uint32 B1SecCntExp:8; //bits[15:8]
Uint32 B2Rsv:8;
Uint32 B3Estatus:8;
}PioSetupDW3;
typedef struct {
Uint32 HW0XferCnt:16; //bits[15:0]
Uint32 HW1Rsv:16;
}PioSetupDW4;
1578
Serial ATA (SATA) Controller
Preliminary
//
required size for Command Table.
//bits[15:8]
//bits[23:16]
//bits[31:24]
//bits[15:8]
//bits[23:16]
//bits[31:24]
//bits[7:0]
//bits[23:16]
//bits[31:24]
//bits[31:16]
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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