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9.2.13 CE-ATA Command Completion Disable Management
The SD/SDIO controller supports CE-ATA features, in particular the detection of command completion
token. When a command that requires a command completion signal (SD_CON[12] CEATA and
SD_CMD[2] ACEN set to 1) is launched, the host system is no longer allowed to emit a new command
in parallel of data transfer unless it is a command completion disable token.
The settings to emit a command completion disable token follow:
•
SD_CON[12] CEATA is set to 1.
•
SD_CON[2] HR set to 1.
•
Clear the SD_ARG register.
•
Write into SD_CMD register with value 0000 0000h.
When a command completion disable token was emitted (that is, SD_STAT[0] CC received), the host
system is again allowed to emit another type of command (for example a transfer abort command
CMD12 to abort transfer).
A critical case can be met when command completion signal disable (CCSD) is emitted during the last
data block transfer, the sequence on command line could be sent very close to command completion
signal (CCS) token sent by the card.
Three cases can be met:
•
CCS is receive just before CCSD is emitted:
An interrupt CIRQ is generated with CCS detection, CCSD is transmitted to card then an interrupt
CC is generated when CCSD ends. In this case, card consider the CCSD sequence.
•
CCS is not generated or generated during the CCSD transfer:
The CCS bit cannot be detected (conflict is not possible as they drive the same level on command
line, then no CIRQ interrupt is generated; besides CC interrupt is generated when CCSD ends).
•
CCS is generated without CCSD token required:
Only the interrupt CIRQ is generated when CCS is detected.
9.2.14 Test Registers
Test registers are available to be compliant with SD Host controller specification. This feature is useful
to generate interrupts manually for driver debugging. The Force Event register (SD_FE) is used to
control the Error Interrupt Status and Auto CMD12 Error Status. The System Test register
(SD_SYSTEST) is used to control the signals that connect to I/O pins when the module is configured in
system test (SD_CON[4] MODE = 1) mode for boundary connectivity verification.
SPRUGX9 – 15 April 2011
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Preliminary
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
© 2011, Texas Instruments Incorporated
Architecture
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