Table of Contents
Advertisement
Supported Use Cases
20.7.3 Interrupt Condition Control
20.7.3.1 USB Core Interrupts
The USB core interrupts are originally generated inside the Mentor core. The core provides enable
registers for each of the three types of interrupts. The INTRTXE register allows enabling of each TX
endpoint interrupt The INTRRXE register allows enabling of each RX endpoint interrupt. The
INTRUSBE register allows enabling of each general USB interrupt. Any enabled interrupt will generate
CPU interrupts in the form of the corresponding interrupt source, the module generated interrupt pulse,
and the interrupt pulse from the Mentor core directly.
To comply with Highlander interrupts, additional logic is built around the core. This adds a mask register
along with mask set and mask clear registers. The USB Interrupt Mask register shows the current mask
value, where each bit enables the corresponding interrupt source in the USB Interrupt Source register.
The USB Interrupt Mask Set register allows writing a '1' in bit positions to enable the corresponding
interrupt source. Those bits written with a '0' will not be modified. The USB Interrupt Mask Clear
register allows writing a '1' in bit positions to disable the corresponding interrupt source. Those bit
written with a '0' will not be modified. The mask is used to enable interrupt sources and generate the
masked interrupt sources which are used to generate the CPU interrupt or by external logic to generate
CPU interrupts.
20.8 Supported Use Cases
The USB Subsystem supports two independent USB Modules where each USB module can operate as
a host or peripheral. When operating as a host, it is capable of interfacing to a single target/peripheral
directly or to multiple targets via hub at low-, full-, or high-speed. When operating as a peripheral, it is
capable of interfacing to a host at a full- or high-speed.
1826
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
