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Architecture
13.2.9.2.1 Interrupt Generation in RC Mode
As per PCI Express Base Specifications, Root Complex ports only receive interrupts. There is no
mechanism to generate interrupts from RC port to EP mode as per PCIe specification. However,
PCIESS does support generation of interrupts from RC to EP. The behavior is similar to generation and
reception of MSI interrupts in RC mode except for the fact that this functionality is enabled in EP mode
as well.
The RC device can perform a memory write into the MSI IRQ register over the PCIe link to generate
one of 32 EP interrupts. Note that the PCIESS will follow PCIe MSI rules and will not necessarily
accumulate multiple writes to the same MSI vector. Only one of such writes is guaranteed to be
processed and subsequent writes on the same vector arriving before the interrupt status is cleared may
be lost.
13.2.9.2.2 Interrupt Generation in EP Mode
When PCIESS is operating as an EP, either the legacy interrupts or the MSI interrupts can be triggered
to the upstream ports (eventually leading to an interrupt in RC device). As per PCIe Specifications,
each PCIe function may generate only one of the Legacy or MSI interrupt types as decided during
configuration period.
Legacy Interrupt Generation in EP Mode
The endpoint can trigger generation of a PCI Legacy Interrupt at the Root Complex via an in-band
Assert_INTx / Deassert_INTx PCIe Message. The actual interrupt that is generated on RC port is
based on the configuration of the EP that generates the interrupt and it could be one of INTA, INTB,
INTC or INTD. See Interrupt related registers in configuration space registers.
To generate an interrupt, following steps are required:
1. Legacy interrupt generation should be enabled via EP_LEGACY_CONFIG register.
2. Write 1h to EP_IRQ_SET register to enable the legacy interrupt.
3. An ASSERT INTA/B/C/D message is automatically sent.
4. Write 1h to EP_IRQ_CLR register to disable the legacy interrupt by sending a DEASSERT INT
A/B/C/D message.
Once an assert message has been generated, it cannot be generated again until a deassert
message is generated. Thus, only one interrupt can be pending at a time. The pending status can
be checked in EP_IRQ_STATUS register.
Note that the interrupt messaging mechanism makes it unfeasible to guarantee a time of delivery of
the interrupt unlike in conventional designs where the interrupt line is often electrically connected to
the final destination.
There is no hardware input port provided that will allow generation of legacy interrupts on the EP
port.
MSI Interrupt Generation in EP Mode
MSI Interrupts are generated by a PCIe Write transaction that performs a 32-bit memory write to a
pre-determined address with a pre-determined data. The PCIe system software configures the
address and the data that is to be used in the memory write transaction at the time of initialization of
the EP device. The MSI scheme supports multiple interrupts and each device can request up to 32
interrupt vectors even though the allotted interrupts may be less than the requested number.
To generate MSI interrupts, the following steps need to be taken:
1. Ensure that the MSI support has been enabled in the device.
2. Read the value of MSI Address Register in the local PCIe configuration space.
3. Read the value of MSI Data Register in the local PCIe configuration space.
4. Determine the number of MSI vectors allocated (and the number requested) to the device.
5. Depending upon the number of MSI interrupts allocated, issue a Memory Write transaction with
the address same as MSI Address Register and Data same as MSI Data Register. In the data,
the LSBs can be modified to reflect appropriate MSI event that needs to be notified to Root
Complex.
6. The Memory Write transaction can also be optionally routed through the outbound address
translation interface if the destination PCIe address is not directly accessible.
1294
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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