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To ensure that a coherent value is read inside WDT_WCRR, the first read access is to the lower 16 bits
(offset = 8h), followed by read access to the upper 16 bits (offset = Ah).
18.2.11 Watchdog Timer Interrupt Generation
When an interrupt source occurs, the interrupt status bit (the WDT_WIRQSTAT[0] EVENT_OVF or
WDT_WIRQSTAT[1] EVENT_DLY bit) is set to 1. The output interrupt line (WDTi_IRQ) is asserted
(active low) when status (the EVENT_xxx bit) and enable (the xxx_IT_ENA bit) flags are set to 1; the
order is not relevant. Writing 1 to the enable bit (the status is already set at 1) also triggers the interrupt
in the normal order (enable first, status next). The pending interrupt event is cleared when the set
status bit is overwritten by a value of 1 by a write command in the WDT_WIRQSTAT register. Reading
the WDT_WIRQSTAT register and writing the value back allows a fast interrupt acknowledge process.
The watchdog timer issues an overflow interrupt if this interrupt is enabled in the watchdog interrupt
enable register (WDT_WIRQENSET[0] OVF_IT_ENA = 1). When the overflow occurs, the interrupt
status bit (the WDT_WIRQSTAT[0] EVENT_OVF bit) is set to 1. The output interrupt line (WDT_IRQ) is
asserted (active low) when status (EVENT_OVF) and enable (OVF_IT_ENA) flags are set to 1; the
order is not relevant. This interrupt can be disabled by setting the WDT_WIRQENCLR[0] OVF_IT_ENA
bit to 1.
The watchdog can issue the delay interrupt if this interrupt is enabled in the interrupt enable register
(WDT_WIRQENSET[1] DLY_IT_ENA = 1). When the counter is running and the counter value matches
the value stored in the delay configuration register (WDT_WDLY), the corresponding interrupt status bit
is set in the watchdog status register (WDT_WIRQSTAT) and the output interrupt line is asserted
(active low) when the flag (EVENT_DLY) and enable (DLY_IT_ENA) bits are 1 in the WDT_WIRQSTAT
and WDT_WIRQENSET registers, respectively; the order (normally enable, then flag), is not relevant.
This interrupt can be disabled by setting the WDT_WIRQENCLR[1] DLY_IT_ENA bit to 1.
NOTE: Writing 0 to the WDT_WIRQSTAT[0] EVENT_OVF bit or the WDT_WIRQSTAT[1]
EVENT_DLY bit has no effect.
The two clock domains are resynchronized because the interrupt event is generated on the functional
clock domain (WDTi_FCLK) during the updating of the interrupt status register (WDT_WIRQSTAT).
The WDT_WDLY register is used to specify the value of the delay configuration register. The delay time
to interrupt is the difference between the reload value stored in the counter load register (WDT_WLDR)
and the programmed value in this register (WDT_WDLY).
Use the following formula to estimate the delay time:
Delay time period = (WDT_WDLY – WDT_WLDR + 1) × Timer clock period × Clock divider
Where:
•
Timer clock period = 1/(Timer clock frequency)
•
Clock divider = 2PTV
If the counter value (WDT_WCRR) reaches the programmed value (WDT_WDLY), the status bit
(EVENT_DLY) gets set in the interrupt status register (WDT_WIRQSTAT), and an interrupt occurs if the
corresponding enable bit is set in the interrupt enable register (WDT_WIRQENSET).
If the reload event occurs (after a triggering sequence or after a reset
sequence) before reaching the programmed value (WDT_WDLY[31:0]
WDLY_VALUE), no interrupt is generated.
Also, no interrupt is generated if the value programmed in the delay
configuration register (WDT_WDLY) is less than the value stored in the
counter load register (WDT_WLDR).
SPRUGX9 – 15 April 2011
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Preliminary
CAUTION
© 2011, Texas Instruments Incorporated
Architecture
1665
Watchdog Timer
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