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Use Case
The inbound memory accesses received by PCIESS on the serial link are initiated by remote PCIe End
Points that are capable of bus mastership. Such accesses are converted to bus transactions on
PCIESS master port and once a Response/Completion is received, the PCIESS sends data/response
back to the PCIe bus master over the serial links. Typically, the inbound accesses will be targeted to
memory space resident on the bus side of the RC port. The locations to which inbound memory
accesses map are determined by software. The software must inform the remote devices about what
protocol is to be followed so that the remote device will access the relevant memory regions to read or
write data/control information. Not all End Points have the capability to initiate inbound accesses.
An inbound access cannot cross a 4 KB boundary as per PCIe specifications. In addition, any access
that spans a 128 byte boundary in the device memory map can get split into two transactions at the 128
byte boundary.
13.3.1.4 I/O Accesses
I/O accesses are optional in PCI Express. In PCIESS, these accesses can be made through a 4KB
memory space and a programmable register. All accesses made to the 4KB space become IO
accesses and the IO Base register determines the target address for such accesses. The IO accesses
cannot be for more than 32-bits of data aligned at 4 byte boundary.
13.3.2 PCIe End Point
When the PCIESS is desired to operate as an Endpoint (EP), the following initialization sequence is
recommended.
13.3.2.1 Initialization Sequence
Upon de-assertion of reset, the PCIESS is configured as End Point by chip level setting of PCIESS
inputs. Before a Root Complex is allowed to access the configuration space of the end point, the
following initialization sequence should be followed:
1. Configure PCIe Mode of operation for EP Mode by programming PCIE_CFG.PCIE_DEVTYPE with
a value of 0.
2. Bring PCIESS out of reset through the device level reset controller.
3. Enable and configure PCIe Clock (See PCIE_CFG Register Description). Note: The Default PLL
Multiplier configuration value (PCIE_CFG.CFG_PLL= 1C9h) is most likely to be used if using a
100 MHz input clock source.
4. Wait for the PCIe PHY PLL to lock; wait for PCIe PLL Status (PCIE_CFG.PCIE_STSPLL) to change
to '1'.
5. Insure that the link is idle. Disable link training by de-asserting the LTSSM Enable bit in PCIESS
Control Register. Upon reset, the LTSSM Enable is de-asserted automatically by hardware,
CMD_STATUS.LTSSM_EN is 0.
6. Program the configuration registers in the PCIESS to desired values.
7. Initiate link training can be initiated by asserting LTSSM Enable bit in PCIESS Control Register;
programming CMD_STATUS.LTSSM_EN with a 1.
8. Insure link training completion and success by observing DEBUG0.LTSSM_STATE field change to
11h.
9. If further configuration register initialization is required, the Application Request Retry bit should be
set. This will lead to incoming accesses to be responded with the retry response. This feature allows
slow devices extra time before the Root Port assumes the devices to be inactive. Once
programming is complete, de-assert Application Request Retry field to allow transactions from the
Root Complex.
10. Once configuration setup is complete, DMA transactions can begin.
11. Inbound PCIe transactions will arrive at the master port of the PCIESS End Point. These will be
responded to by the target slave devices and the PCIESS will relay the response back to the PCIE
device that initiated the transaction.
12. Outbound PCIe transactions will be targeted to the slave port of the PCIESS End Point. These
transactions will be serviced only if the PCIESS End Point has been given Bus Master Capability by
the Root Complex.
1304
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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