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16.3.4 Example of DMA Read Transfer
void performDmaRead() {
// READ DMA
/*
When performing the Non-Queued Command "Read DMA" the following captures the FISes that are
communicated between Host (HBA) and Device (SpeedBridge or SATA Drive).
HBA ==> Device
field).
Device ==> HBA
Command Table).
Device ==> HBA
If need to capture Interrupt (just have only the Flag set) at:
Global Level (IS Register), need to enable P0IE.Interrupt field.
Port Level (No Enable bit needs to be set. P0IS will be set if D2H FIS DW0.Byte1.bit6 is
set).
If need to generate Interrupt at:
Global Level (enable interrupt by setting GHC.IE bit field and P0IE.xxx should be set to
enable particular interrupt). Port Level interrupt handling is a subset of Global Level.
Port Level (So long as Global Level interrupt is not enabled, GHC.IE is set, Interrupt will
not be sent to CPU just from Port Level only).
*/
// Read from Disk
cmdSlot2Use=1;
associateSysMem2Hba(cmdSlot2Use);
Table
//Initialize PRD Data Buffer Memory
//
initMemory((Uint32 *)&prdTableDataBuff[cmdSlot2Use],
(sata_input_prdLength*DATABUFFERLEN/4), 0xDEADBEEF, 0x00000000);
// Configure Device 28 bit LBA Address (Start Address for Rd/Wr Transfer);
Dev28bitLbaAddress
setupCfisEntriesForDataRdWr(&CmdLists[cmdSlot2Use], DATA_DIR_RD, DMA_PROTOCOL);
Usage: setupCfisEntriesForDataRdWr(CmdListHeader *, DataDir, xferProtocol)
DATA_DIR_WR, xferProtocol = PIO/DMA_PROTOCOL
// Write cfis Data
buildCmdFis(&CmdTable[cmdSlot2Use]);
//getCmdFis(&CmdTable[cmdSlot2Use]);
startCmdListProcessing(); // Stay here if unable to start processing command list.
submitCmd (NON_QUEUED_CMD, cmdSlot2Use); // Usage: CommandType (QUEUED(NON_QUEUED)_CMD,
Command Slot);
if(intHandlingMethod == USE_INT_HANDLER) { //
while(intIsrFlag==0);
intIsrFlag=0;
}
else
while(sataRegs->IS == 0);
is received.
// If P0IS.DPS is set, A PRD with the I bit set has transferred all of its data.
// This bitfield might not bit set for Non-Queued DMA. Applicable for Queued DMA
//while(getRegStatus((Uint32*)&sataRegs->P0IS, AHCI_P0IS_DPS) == 0); //
getRegStatus(ptr2int,field Mask)
while(getRegStatus((Uint32*)&sataRegs->P0CI, (1<<cmdSlot2Use)) == (1<<cmdSlot2Use));
Wait Until P0CI[ChHeader] to be cleared by HBA
// Clears both P0IS and IS register. Only Clears RWC bit fields. So, it is OK for this task.
clearIntOrErrorDiag(INTFIELDS, sataRegs->P0IS);
}
SPRUGX9 – 15 April 2011
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Preliminary
H2D FIS (Command FIS that has the "Read DMA" Command within H2D.Command
Data FIS (Actual Data Requested and pointed by the DMA/PRD Contents within
D2H FIS (Completion Status from Device)
// Associate Sys Memory to CmdList and PRDs to Cmd
= sata_input_startAddress; // 28-Bit LBA Address
© 2011, Texas Instruments Incorporated
// DataDir = DATA_DIR_RD or
USE_POLLING or USE_INT_HANDLER
// Stay here until an interrupt
// Clear P0IS Register
Serial ATA (SATA) Controller
Use Cases
//
//
1591
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