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Architecture
The software can then continue with the normal initialization that is required by the software. The
details and sequence of initialization is documented within the AHCI specification. In general, everything
that is achieved by the Software Initialization has to do with configuring and furnishing resources
needed by the AHCI controller and these tasks include PHY Initialization, allocating structures and
memories for Command Slots, FIS, and Data Memories and concludes by enabling the receive FIS
DMA. The software will then Spin-Up the Device and ensure that a proper Device Detection and Speed
Negotiation has completed prior to enabling the Command DMA.
Note that DMA Configuration/Initialization should take place after Device Detection and Speed
Negotiation. If done earlier, the default value is used (which is the recommended setting) since RESET
removes the user programmed values. The only time it is advisable to change the DMA Configuration is
when you need to prioritize System Resource access. This still has to be done after "PHY Ready"
status is set (in other words, after the device detection and speed negotiation has completed). It also
requires that the Command DMA is not running (P0CMD.ST = 0) when modifying the value of the DMA
Configuration fields.
16.2.12.1 Initialization (Firmware and Software)
Software reads the HBA capabilities register (CAP), ports implemented register (PI), AHCI version
register (VS), global parameter 1 register (GPARAM1R), global parameter 2 register (GPARAM2R),
and the port parameter register (PPARAMR) to obtain information about the subsystem's capabilities.
The software should then take the following steps to configure each port for operation:
1. Do all firmware capability writes.
2. Setup all appropriate structures in memory as per the AHCI specification.
3. Configure the PHY using the port PHY control register (P#PHYCR):
(a) Set the MPY bit field for the PLL multiply factor (multiply value selected should target a 1.5GHz
frequency which is good enough for both GEN1 and GEN2 speeds).
(b) Set LOS = 1 (enable loss of signal detection)
(c) Set ENPLL = 1 (enable the PLL)
4. Set the port command list base address register (P#CLB).
5. Set the port FIS base address register (P#FB).
6. Set appropriate bits in the port command register (P#CMD).
7. Program the port serial ATA control register (P#SCTL).
8. Wait for Device Detection and Speed Negotiation to end.
9. Program the port DMA control register (P#DMACR).
10. Enable the appropriate interrupts.
11. Enable FIS reception in P#CMD.
12. Spin-up the device(s), if necessary.
16.2.12.2 Issuing a Command
Once the host and device are configured, perform the following steps to issue a command:
1. Create the appropriate FIS in system memory.
2. Create the PRD.
3. Queue the command to the command queue list (location specified by the port command list base
address register (P#CLB).
For detailed information, see the AHCI Specification Version 1.1.
1572
Serial ATA (SATA) Controller
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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