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Registers
Table 7-12. I2C Wakeup Enable Register (I2C_WE) Field Descriptions (continued)
Bit
Field
9
AAS_WE
8
BF_WE
7
Reserved
6
STC_WE
5
GC_WE
4
Reserved
3
DRDY_WE
2
ARDY_WE
1
NACK_WE
874
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Value
Description
Address as slave IRQ wakeup enable. This read/write bit is used to enable or disable wakeup
signal generation when I2C module is in idle mode, and external master addresses the I2C
module as a slave. This allows for the module to inform the CPU that it can check which of the
own addresses was used by the external master to access the I2C core.
0
Addressed as slave wakeup disabled
1
Addressed as slave wakeup enabled
Bus free IRQ wakeup enable. This read/write bit is used to enable or disable wakeup signal
generation when I2C module is in idle mode and the I2C bus became free. This allows for the
module to inform the CPU that it can initiate its own transfer on the I2C line.
0
Bus Free wakeup disabled
1
Bus Free wakeup enabled
0
Reserved
Start condition IRQ wakeup set. This read/write bit is used to enable or disable wakeup signal
generation when I2C module is in idle mode (with the functional clock inactive) and a possible
start condition is detected on the I2C line. The STC WakeUp is generated only if the
I2C_SYSC.ClockActivity field indicates that the functional clock can be disabled. Note that if the
functional clock is not active, the start condition is asynchronously detected (no filtering and
synchronization is used). For this reason, it is possible that the signalized start condition to be a
glitch.
If the functional clock cannot be disabled (I2C_SYSC.ClockActivity = 10 or 11), the programmer
should not enable this wakeup, since the module has other synchronously detected WakeUp
event that might be used to exit from idle mode, only if the detected transfer is accessing the I2C
module.
0
Start condition wakeup disabled
1
Start condition wakeup enabled
General call IRQ wakeup enable. This read/write bit is used to enable or disable wakeup signal
generation when I2C module is in idle mode and a general call is received on I2C line.
0
General call wakeup disabled
1
General call wakeup enabled
0
Reserved
Receive/Transmit data ready IRQ wakeup enable. This read/write bit is used to enable or disable
wakeup signal generation when I2C module is involved into a long transfer and no more registers
accesses are performed on the interface (for example module are set in F/S I2C master
transmitter mode and FIFO is full). If in the middle of such a transaction, the FIFO buffer needs
more data to be transferred, CPU must be informed to write (in case of transmitter mode) or read
(if receiver mode) in/from the FIFO.
0
Transmit/receive data ready wakeup disabled
1
Transmit/receive data ready wakeup enabled
Register access ready IRQ wakeup enable. This read/write bit is used to enable or disable
wakeup signal generation when I2C module is involved into a long transfer and no more registers
accesses are performed on the interface (for example the module is set in F/S I2C master
transmitter mode and FIFO is full). If the current transaction is finished, the module needs to
inform CPU about transmission completion.
0
Register access ready wakeup disabled
1
Register access ready wakeup enabled
No acknowledgment IRQ wakeup enable. This read/write bit is used to enable or disable wakeup
signal generation when I2C module is involved into a long transfer and no more registers
accesses are performed on the interface (for example the module is set in F/S I2C master
transmitter mode and FIFO is full). If in the middle of such of a transaction a Not Acknowledgment
event is raised, the module needs to inform CPU about transmission error.
0
Not Acknowledge wakeup disabled
1
Not Acknowledge wakeup enabled
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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