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Architecture
4. Start the respective serial clocks ACLKX and/or ACLKR. This step can be skipped if external serial
clocks are used and they are running:
(a) Take the respective internal serial clock divider(s) out of reset by setting the RCLKRST bit for
the receiver and/or the XCLKRST bit for the transmitter in GBLCTL. All other bits in GBLCTL
should be left at the previous state.
(b) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
GBLCTL before you proceed.
5. Setup data acquisition as required:
(a) If DMA is used to service the McASP, set up data acquisition as desired and start the DMA in
this step, before the McASP is taken out of reset.
(b) If CPU interrupt is used to service the McASP, enable the transmit and/ or receive interrupt as
required.
(c) If CPU polling is used to service the McASP, no action is required in this step.
6. Activate serializers.
(a) Before starting, clear the respective transmitter and receiver status registers by writing
XSTAT = FFFFh and RSTAT = FFFFh.
(b) Take the respective serializers out of reset by setting the RSRCLR bit for the receiver and/or the
XSRCLR bit for the transmitter in GBLCTL. All other bits in GBLCTL should be left at the
previous state.
(c) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
GBLCTL before you proceed.
7. Verify that all transmit buffers are serviced. Skip this step if the transmitter is not used. Also, skip
this step if time slot 0 is selected as inactive (special cases, see
As soon as the transmit serializer is taken out of reset, XDATA in the XSTAT register is set,
indicating that XBUF is empty and ready to be serviced. The XDATA status causes an DMA event
AXEVT to be generated, and can cause an interrupt AXINT to be generated if it is enabled in the
XINTCTL register.
(a) If DMA is used to service the McASP, the DMA automatically services the McASP upon
receiving AXEVT. Before proceeding in this step, you should verify that the XDATA bit in the
XSTAT is cleared to 0, indicating that all transmit buffers are already serviced by the DMA.
(b) If CPU interrupt is used to service the McASP, interrupt service routine is entered upon the
AXINT interrupt. The interrupt service routine should service the XBUF registers. Before
proceeding in this step, you should verify that the XDATA bit in XSTAT is cleared to 0, indicating
that all transmit buffers are already serviced by the CPU.
(c) If CPU polling is used to service the McASP, the XBUF registers should be written to in this step.
8. Release state machines from reset.
(a) Take the respective state machine(s) out of reset by setting the RSMRST bit for the receiver
and/or the XSMRST bit for the transmitter in GBLCTL. All other bits in GBLCTL should be left at
the previous state.
(b) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
GBLCTL before you proceed.
9. Release frame sync generators from reset. Note that it is necessary to release the internal frame
sync generators from reset, even if an external frame sync is being used, because the frame sync
error detection logic is built into the frame sync generator.
(a) Take the respective frame sync generator(s) out of reset by setting the RFRST bit for the
receiver, and/or the XFRST bit for the transmitter in GBLCTL. All other bits in GBLCTL should be
left at the previous state.
(b) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
GBLCTL before you proceed.
10. Upon the first frame sync signal, McASP transfers begin. The McASP synchronizes to an edge on
the frame sync pin, not the level on the frame sync pin. This makes it easy to release the state
machine and frame sync generators from reset.
(a) For example, if you configure the McASP for a rising edge transmit frame sync, then you do not
need to wait for a low level on the frame sync pin before releasing the McASP transmitter state
machine and frame sync generators from reset.
1060
Multichannel Audio Serial Port (McASP)
Preliminary
© 2011, Texas Instruments Incorporated
Figure
10-20, second waveform).
SPRUGX9 – 15 April 2011
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