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Architecture
10.2.6.2.2 Special 384 Slot TDM Mode for Connection to External DIR
The McASP receiver also supports a 384 time slot TDM mode (DIR mode), to support S/PDIF, AES-3,
IEC-60958 receiver ICs whose natural block (block corresponds to McASP frame) size is 384 samples.
The advantage to using the 384 time slot TDM mode is that interrupts may be generated synchronous
to the S/PDIF, AES-3, IEC-60958, such as the last slot interrupt.
The receive TDM time slot register (RTDM) should be programmed to all 1s during reception of a DIR
block. Other TDM functionalities (for example, inactive slots) are not supported (only the slot counter
counts the 384 subframes in a block).
To receive data in the DIR mode, the following pins are typically needed:
•
ACLKR - receive bit clock.
•
AFSR - receive frame sync (or commonly called left/right clock). In this mode, AFSR should be
connected to a DIR which outputs a start of block signal, instead of LRCLK.
•
One or more serial data pins, AXRn, whose serializers have been configured to receive.
For this special DIR mode, the control registers can be configured just as for TDM mode, except set
RMOD in AFSRCTL to 384 to receive 384 time slots.
10.2.6.3 Digital Audio Interface Transmit (DIT) Transfer Mode
In addition to the TDM and burst transfer modes, which are suitable for transmitting audio data between
ICs inside the same system, the digital audio interface transmit (DIT) transfer mode of the McASP also
supports transmission of audio data in the S/PDIF, AES-3, or IEC-60958 format. These formats are
designed to carry audio data between different systems through an optical or coaxial cable. The DIT
mode only applies to serializers configured as transmitters, not receivers. Refer to
a description of the S/PDIF format.
10.2.6.3.1 Transmit DIT Encoding
The McASP operation in DIT mode is basically identical to the 2 time slot TDM mode, but the data
transmitted is output as a biphase mark encoded bit stream, with preamble, channel status, user data,
validity, and parity automatically stuffed into the bit stream by the McASP. The McASP includes
separate validity bits for even/odd subframes and two 384-bit RAM modules to hold channel status and
user data bits.
The transmit TDM time slot register (XTDM) should be programmed to all 1s during DIT mode. TDM
functionality is not supported in DIT mode, except that the TDM slot counter counts the DIT subframes.
To transmit data in the DIT mode, the following pins are typically needed:
•
AHCLKX - transmit high-frequency master clock.
•
One or more serial data pins, AXRn, whose serializers have been configured to transmit.
AHCLKX is optional (the internal clock source may be used instead), but if used as a reference, the
processor provides a clock check circuit that continually monitors the AHCLKX input for stability.
If the McASP is configured to transmit in the DIT mode on more than one serial data pin, the bit
streams on all pins will be synchronized. In addition, although they will carry unique audio data, they will
carry the same channel status, user data, and validity information.
The actual 24-bit audio data must always be in bit positions 23-0 after passing through the first three
stages of the transmit format unit.
1032
Multichannel Audio Serial Port (McASP)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
Section 10.1.6.2
for
SPRUGX9 – 15 April 2011
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