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Table 7-8. I2C Status Raw Register (I2C_IRQSTATUS_RAW) Field Descriptions (continued)
Bit
Field
Value
5
GC
0
1
4
XRDY
0
1
3
RRDY
0
1
SPRUGX9 – 15 April 2011
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Preliminary
Description
General call IRQ status. Set to '1' by core when General call address detected and interrupt signaled
to MPUSS. Write '1' to clear. I2C mode only.
This read/clear only bit is set to 1 by the device if it detects the address of all zeros (8 bits) (general
call). When this bit is set to 1 by the core, an interrupt is signaled to the local host if the interrupt was
enabled. The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no effect.
Note: When this bit is set to 1, AAS also reads as 1.
No general call detected
General call address detected
Value after reset is low.
Transmit data ready IRQ status. Set to '1' by core when transmitter and when new data is requested.
When set to '1' by core, an interrupt is signaled to MPUSS. Write '1' to clear. Transmit mode only (I2C
mode).
This read/clear only bit (XRDY) is set to 1 when the I2C peripheral is a master or slave transmitter, the
CPU needs to send data through the I2C bus, and the module (transmitter) requires new data to be
served. Note that a master transmitter requests new data if the FIFO TX level is below the threshold
(TXTRSH) and the required amount of data remained to be transmitted (I2C_BUFSTAT.TXSTAT) is
greater than the threshold. A slave transmitter requests new data when the FIFO TX level is below the
threshold (if TXTRSH > 1), or anytime there is a read request from external master (for each
acknowledge received from the master), if TXTRSH = 1.
When this bit is set to 1 by the core, an interrupt is signaled to the local host if the interrupt was
enabled. The CPU can also poll this bit (refer to the FIFO Management subsection for details about
XRDY generation). The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no
effect.
Note: If the DMA transmit mode is enabled (I2C_BUF.XDMA_EN is set, together with
I2C_DMATXENABLE_SET), this bit is forced to 0 and no interrupt will be generated; instead, a DMA
TX request to the main DMA controller of the system is generated.
Transmission ongoing
Transmit data ready
Value after reset is low.
Receive mode only (I2C mode).
This read/clear only RRDY is set to 1 when the RX FIFO level is above the configured threshold
(RXTRSH). When this bit is set to 1 by the core, CPU is able to read new data from the I2C_DATA
register. If the corresponding interrupt was enabled, an interrupt is signaled to the local host. The CPU
to read the received data in I2C_DATA register can also poll this bit (refer to the FIFO Management
subsection for details about RRDY generation).
The CPU can only clear this bit by writing a 1 into this register. A write 0 has no effect.
If the DMA receive mode is enabled (I2C_BUF.RDMA_EN is set, together with
I2C_DMARXENABLE_SET), this bit is forced to 0 and no interrupt will be generated; instead a DMA
RX request to the main DMA controller of the system is generated.
Receive FIFO threshold not reached
Receive data ready for read (RX FIFO threshold reached)
Value after reset is low.
© 2011, Texas Instruments Incorporated
Inter-Integrated Circuit (I2C) Controller Module
Registers
865
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