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Architecture
11.2.8.5.20 Set the SRG Clock Divide-Down Value
CLKGDV bit field (SRGR1_REG[7:0]) is used to set the sample rate generator clock divide-down value.
The first divider stage generates the serial data bit clock from the input clock. This divider stage utilizes
a counter, preloaded by CLKGDV, that contains the divide ratio value.
The output of the first divider stage is the data bit clock, which is output as CLKG and which serves as
the input for the second and third stages of the divider.
CLKG has a frequency equal to 1/(CLKGDV + 1) of sample rate generator input clock. Thus, the
sample generator input clock frequency is divided by a value between 1 and 256. The CLKG duty cycle
is 50%.
11.2.8.5.21 Set the SRG Clock Synchronization Mode
GSYNC bit (SRGR2_REG[15]) is used to set the SRG clock synchronization mode.
11.2.8.5.22 Set the SRG Clock Mode (choose an input clock)
SCLKME bit (PCR_REG[7]) and CLKSM bit (SRGR2_REG[13]) are used to set the SRG clock mode.
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter,
or both, but CLKG is derived from an input clock.
11.2.8.5.23 Set the SRG Input Clock Polarity
CLKSP bit (SRGR2_REG[14]), CLKXP bit (PCR_REG[1]) and CLKRP bit (PCR_REG[0]) are used to
set the SRG input clock polarity.
The sample rate generator can produce a clock signal (CLKG) and a frame–synchronization signal
(FSG) for use by the receiver, the transmitter, or both. To produce CLKG and FSG, the sample rate
generator must be driven by an input clock signal derived from the McBSP_FCLK clock or from an
external clock on the McBSP.CLKS, McBSP.CLKX, or McBSP.CLKR pin. If you use a pin, choose a
polarity for that pin by using the appropriate polarity bit (CLKSP for the McBSP.CLKS pin, CLKXP for
the McBSP.CLKX pin, CLKRP for the McBSP.CLKR pin). The polarity determines whether the rising or
falling edge of the input clock generates transitions on CLKG and FSG.
11.2.8.6 Transmitter Configuration
To configure the McBSP transmitter, perform the following procedure:
1. Place the McBSP transmitter in reset
2. Program the McBSP registers for the desired transmitter
3. Take the transmitter out of reset
These three steps are detailed in the following subsections.
11.2.8.6.1 Programming the McBSP Registers for the Desired Transmitter Operation
The following is a list of important tasks to be performed when you are configuring the McBSP
transmitter. Each task corresponds to one or more McBSP register bit fields.
Global behavior:
1. Set the transmitter pins to operate as McBSP pins.
2. Enable/disable the digital loop back mode.
3. Enable/disable the analog loop back mode.
4. Enable/disable the synchronous transmit-receive mode.
5. Enable/disable transmit multichannel selection.
1166
Multichannel Buffered Serial Port (McBSP)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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