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Basic Programming Model
7. After the return of the subroutine, the ISR sets the NEWIRQAGR/NEWFIQAGR bit to enable the
processing of subsequent pending IRQs/FIQs and to restore ARM context in the following code.
Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are
done before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure
that the IRQ/FIQ line is de-asserted before IRQ/FIQ enabling. After that, the INTC processes any
other pending interrupts or deasserts the IRQ/FIQ signal if there is no interrupt.
; INTCPS_CONTROL register address
INTCPS_CONTROL_ADDR .word 0x48200048;
NEWIRQAGR/NEWFIQAGR bit mask to set only the NEWIRQAGR/NEWFIQAGR bit
NEWIRQAGR_MASK/NEWFIQAGR_MASK .equ 0x01/0x02
IRQ_ISR_end/FIQ_ISR_end:
; Allow new IRQs/FIQs at INTC side
; The INTCPS_CONTROL register is a write only register so no need to write back others bits
MOV R0, #NEWIRQAGR_MASK/NEWFIQAGR_MASK ; Get the NEWIRQAGR/NEWFIQAGR bit position
LDR R1, INTCPS_CONTROL_ADDR
STR R0, [R1] ; Write the NEWIRQAGR/NEWFIQAGR bit to allow new IRQs/FIQ
; Data Synchronization Barrier MOV R0, #0
MCR P15, #0, R0, C7, C10, #4
; restore critical context
MSR SPSR, R11 ; Restore the SPSR from R11
LDMFD SP!, {R0-R12, LR} ; Restore working registers and
; Return after handling the interrupt
SUBS PC, LR, #4
8. After the ISR return, the ARM automatically restores its context as follows:
CPSR = SPSR
PC = LR
Figure 8-4
shows the IRQ/FIQ processing sequence from the originating device peripheral module to
the main program interruption.
The priority sorting mechanism is frozen during an interrupt processing sequence. If an interrupt
condition occurs during this time, the interrupt is not lost. It is sorted when the
NEWIRQAGR/NEWFIQAGR bit is set (priority sorting is reactivated).
910
Interrupt Controller
Preliminary
© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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