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9.4.1 IP Revision Identifier Register (SD_HL_REV)
This register holds the IP Revision Identifier (X.Y.R) information.
31
30
29
28
SCHEME
Reserved
R-0
R-0
15
R_RTL
R-0
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
9.4.2 IP Module Hardware Configuration Register (SD_HL_HWINFO)
This register provides information about the IP module's hardware configuration, i.e. typically the
module's HDL generics (if any).
31
15
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
9.4.3 Clock Management Configuration (SD_HL_SYSCONFIG)
This register provides information about the clock management configuration.
31
15
Reserved
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
SPRUGX9 – 15 April 2011
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Preliminary
Figure 9-29. SD_HL_REV Register
27
10
X_MAJOR
R-x
Figure 9-30. SD_HL_HWINFO Register
Reserved
R-0
Figure 9-31. SD_HL_SYSCONFIG Register
R-0
© 2011, Texas Instruments Incorporated
FUNC
R-20h
8
7
6
5
CUSTOM
R-0
Reserved
R-0
Reserved
R-0
6
5
4
3
STANDBYMODE
IDLEMODE
R/W-2h
R/W-2h
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Registers
16
0
Y_MINOR
R-x
16
2
1
0
MEM_SIZE
MADMA_EN
R-0
R-x
16
2
1
0
FREEEMU
SOFTRESET
R/W-0
R/W-0
963
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