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Architecture
Only one SPI word can be transmitted/received per OCP bus access to write/read the transmit or
receive register.
12.2.6.2 FIFO Buffer Enabled
The DMA Read request line is asserted when the channel is enabled and a number of bytes defined in
MCSPI_XFERLEVEL[AFL] bit field is hold in FIFO buffer for the receive register of the channel. DMA
Read request can be individually masked with the bit DMAR of the register MCSPI_CH(I)CONF. The
DMA Read request line is de-asserted (OCP compliant as defined in [1]) on the first SPI word read
completion of the receive register of the channel. No new DMA request will be asserted again as soon
as user has not performed the right number of read accesses defined by MCSPI_XFERLEVEL[AFL] it
is under user responsibility.
The DMA Write request line is asserted when the channel is enabled and the number of bytes hold in
FIFO buffer is below the level defined by the MCSPI_XFERLEVEL[AEL] bit field. DMA Write request
can be individually masked with the bit DMAW of the register MCSPI_CH(I)CONF. The DMA Write
request line is de-asserted (OCP compliant as defined in [1]) on load completion of the first SPI word in
the transmitter register of the channel. No new DMA request will be asserted again as soon as user has
not performed the right number of write accesses defined by MCSPI_XFERLEVEL[AEL] it is under user
responsibility.
Only one SPI word can be transmitted/received per OCP bus access to write/read the transmit or
receive FIFO.
12.2.6.3 DMA 256 Bit Aligned Addresses
The controller has two registers MCSPI_DAFTX and MCSPI_DAFRX only used with an enabled
channel which manages the FIFO to be compliant the a DMA handler providing only 256 bit aligned
addresses.
This features is activated when the bit field MCSPI_MODULCTRL[8] FDAA is set to '1' and only one
enabled channel have its bit field MCSPI_CH(I)CONF[27] FFE(I)W or MCSPI_CH(I)CONF[28] FFE(I)R
enabled.
In this case the registers MCSPI_TX(I) and MCSPI_RX(I) are not used and datas are managed through
registers MCSPI_DAFTX and MCSPI_DAFRX.
12.2.7 Emulation Mode
The MReqDebug input differentiates a regular access of a processor (application access), from an
emulator access.
Application access: MReqDebug = 0
In functional mode, the consequences of a read of a receiver register MCSPI_RX(i) are the following:
•
The source of an RXi_Full event in the MCSPI_IRQSTATUS register is removed, if it was enabled in
the MCSPI_IRQENABLE register.
•
The RXiS status bit in the MCSPI_IRQSTATUS register is cleared.
•
In master mode, depending on the round robin arbitration, and the transmitter register state, the
channel may access to the shift register for transmission/reception.
Emulator access: MReqDebug = 1
In emulation mode, McSPI behavior is the same as in functional mode but a read of a receiver register
MCSPI_RX(i) is not intrusive:
•
MCSPI_RX(i) is still considered as not read. When the FIFO buffer is enabled, pointers are not
updated.
•
The source of an RXi_Full event in the MCSPI_IRQSTATUS register is not removed. The RXiS
status bit in the MCSPI_CH(i)STAT register is held steady.
In emulation mode, as in functional mode, based on the ongoing data transfers, the status bits of the
MCSPI_CH(i)STAT register may be optionally updated, the interrupt and DMA request lines may be
optionally asserted.
1246
Multichannel Serial Port Interface (McSPI)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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