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Table 7-20. Buffer Configuration Register (I2C_BUF) Field Descriptions (continued)
Bit
Field
13-8
RXTRSH
7
XDMA_EN
6
TXFIFO_CLR
5-0
TXTRSH
SPRUGX9 – 15 April 2011
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Preliminary
Value
Description
0-3Fh
Threshold value for FIFO buffer in RX mode. The receive threshold value is used to specify the
trigger level for data receive transfers. The value is specified from the OCP point of view.
0
Receive Threshold value = 1
1
Receive Threshold value = 2
-
-
3Fh
Receive Threshold value = 64
Value after reset is 00h.
For the FIFO management description, see the FIFO Management subsection.
Note1: programmed threshold cannot exceed the actual depth of the FIFO.
Note2: the threshold must not be changed while a transfer is in progress (after STT was
configured or after the module was addressed as a slave).
Transmit DMA channel enable. When this bit is set to 1, the transmit DMA channel is enabled and
the transmit data ready status (I2C_IRQSTATUS_RAW: XRDY) bit is forced to 0 by the core.
0
Transmit DMA channel disabled
1
Transmit DMA channel enabled
Value after reset is low.
Transmit FIFO clear. When set, transmit FIFO is cleared (hardware reset for TX FIFO). This bit is
automatically reset by the hardware. During reads, it always returns 0.
0
Normal mode
1
Tx FIFO is reset
Value after reset is low.
0-3Fh
Threshold value for FIFO buffer in TX mode. The Transmit Threshold value is used to specify the
trigger level for data transfers. The value is specified from the OCP point of view.
0
Transmit Threshold value = 1
1
Transmit Threshold value = 2
-
-
3Fh
Transmit Threshold value = 64
Value after reset is 00h
Note1: programmed threshold cannot exceed the actual depth of the FIFO.
Note2: the threshold must not be changed while a transfer is in progress (after STT was
configured or after the module was addressed as a slave).
© 2011, Texas Instruments Incorporated
Inter-Integrated Circuit (I2C) Controller Module
Registers
883
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