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11.2.8.5.3 Set the Receiver Pins to Operate as McBSP Pins
The RIOEN bit (PCR_REG[12]) determines whether the receiver pins are McBSP pins or
general–purpose I/O pins.
11.2.8.5.4 Enable/Disable the Synchronous Transmit-Receive Mode
The ALBCTRLRX input pin is used to configure the synchronous transmit-receive mode.
The ALBCTRLRX [0] controls the multiplexer which connects the functional receive input clock (CLKR
is connected to the CLKX input pin CLKXI when ALBCTRLRX[0] = 1).
The ALBCTRLRX[1] controls the multiplexer which connects the receive frame synchronization (FSR is
connected to the FSX input pin FSXI when ALBCTRLRX[1] = 1).
11.2.8.5.5 Enable/Disable the Analog Loop Back Mode
The ALB bit (SPCR1_REG[15]) determines whether the analog loop-back mode is on or off.
In the analog loop-back mode, the receive signals are connected internally through multiplexers to the
corresponding transmit loop back signals (DR is connected to transmit loop back data on DXI pin, FSR
is connected to FRX input pin FSXI, and CLKR is connected to the CLKX input pin CLKXI). This mode
allows testing of serial port; the McBSP receives the data it transmits. This loop back mode is done
through pads testing also the IO buffers.
11.2.8.5.6 Enable/Disable the Digital Loop Back Mode
The DLB bit (XCCR_REG) determines whether the digital loop-back mode is on or off. In the digital
loop-back mode, the receive signals are connected internally through multiplexers to the corresponding
transmit signals (DR is connected to transmit data on DX output pin DXO, FSR is connected to FRX
output pin FSXO, and CLKR is connected to the CLKX output pin CLKXO). This mode allows testing of
serial port; the McBSP receives the data it transmits. This loop back mode is not done through pads, all
output signals being disabled (CLKREN, CLKXEN, FSREN, FSRXEN, DXEN are not active).
Note that in digital loop back mode the sample rate generator and the frame synchronization generator
need to be enabled in order to generate the CLKX and FSX signals.
11.2.8.5.7 Enable/Disable the Receive Multichannel Selection Mode
The RMCM bit (MCR1_REG[0]) determines whether the receive multichannel selection mode is on or
off.
11.2.8.5.8 Choose 1 or 2 Phases for the Receive Frame
The RPHASE bit (RCR2_REG[15]) determines whether the receive data frame has one or two phases.
When dual-phase is selected the number of words per phase must be set to one.
11.2.8.5.9 Set the Receive Word Length(s)
The RWDLEN1 (RCR1_REG[7:5]) and RWDLEN2 (RCR2_REG[7:5]) bit fields determine how many
bits are in each serial word in phase 1 and in phase 2, respectively, of the receive data frame.
Each frame can have one or two phases, depending on the value that you load into the RPHASE bit. If
a single–phase frame is selected, RWDLEN1 selects the length for every serial word received in the
frame. If a dual–phase frame is selected, RWDLEN1 and RWDLEN2 must be cleared to 0 (one word
per phase).
11.2.8.5.10 Set the Receive Frame Length
The RFRLEN1 (RCR1_REG[14:8]) and RFRLEN2 (RCR2_REG[14:8]) bit fields determine how many
serial words are in phase 1 and in phase 2, respectively, of the receive data frame.
The receive frame length is the number of serial words in the receive frame. Each frame can have one
or two phases, depending on value that you load into the RPHASE bit.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Architecture
1159
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