Port Interrupt Status Register (P#Is); Port Interrupt Status Register (P#Is) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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16.4.22 Port Interrupt Status Register (P#IS) (# = 0 or 1)
The port interrupt status register (P#IS) is used to generate SATASS interrupts when any of the bits are
set. Bits in this register are set by some internal conditions, and cleared by software writing ones in the
positions it wants to clear. This register is reset on Global reset.
The P#IS register is shown in
31 30 29 28
Rsvd TFES HBFS HBDS
R-0 R/W1C-0 R/W1C-0 R/W1C-0
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 16-25. Port Interrupt Status Register (P#IS) Field Descriptions
Bit Field Value
31 Reserved 0
30 TFES 0-1
29 HBFS 0-1
28 HBDS 0-1
27 IFS 0-1
26 INFS 0-1
25 Reserved 0
24 OFS 0-1
23 IPMS 0-1
22 PRCS 0-1
21-8 Reserved 0
SPRUGX9 – 15 April 2011
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Preliminary
Figure 16-23 and described in
Figure 16-23. Port Interrupt Status Register (P#IS)
27 26 25 24
IFS INFS Rsvd OFS
R/W1C-0 R/W1C-0 R-0 R/W1C-0
8
R-0
Description
Reserved. Since no dedicated pins for CPD detection/control exist for the device, this bit is reserved. If
need to support this feature, use of GPIO is recommended.
Task File Error Status. This bit is set whenever the P0TFD register is updated by the device and the
error bit (P0TFD.STS[0]) is set.
Host Bus Fatal Error Status. This bit is set when SATASS bus master detects an ERROR response
from the slave.
Host Bus Data Error Status. This bit is always cleared to 0.
Interface Fatal Error Status. This bit is set if any of the following conditions is detected:
• SYNC escape is received from the device during H2D Register or Data FIS transmission.
• One or more of the following errors are detected during Data FIS transfer: Protocol
(P0SERR.ERR_P), CRC (P0SERR.DIAG_C), Handshake (P0SERR.DIAG_H), PHY Not Ready
(P0SERR.ERR_C).
• Unknown FIS is received with good CRC, but the length exceeds 64 bytes.
• PRD table byte count is zero.
Port DMA transitions to a fatal state until software clears P0CMD.ST bit or resets the interface by way
of Port or Global reset.
Interface Non-fatal Error Status. This bit is set if any of the following conditions is detected:
• One or more of the following errors are detected during non-data FIS transfer: Protocol
(P0SERR.ERR_P), CRC (P0SERR.DIAG_C), Handshake (P0SERR.DIAG_H), PHY Not Ready
(P0SERR.ERR_C).
• Command list underflow during read operation (DMA read) when software builds command table that
has more total bytes than the transaction given to the device.
In both cases, Port operation continues normally. If error is detected during non-data FIS transmission,
this FIS is retransmitted continuously until it succeeds or software times out and resets the interface.
Reserved.
Overflow Status. This bit is set if command list overflow is detected during read or write operation when
software builds a command table that has fewer total bytes than the transaction given to the device.
Port DMA transitions to a fatal state until software clears P0CMD.ST bit or resets the interface by way
of Port or Global reset.
Incorrect Port Multiplier Status. Indicates that the HBA received a FIS from a device whose Port
Multiplier field did not match what was expected.
This bit may be set during enumeration of devices on a Port Multiplier due to the normal Port Multiplier
enumeration process. The software should only use the IPMS bit after enumeration is complete on the
Port Multiplier.
PHY Ready Change Status. When set to 1, indicates the internal PHY Ready signal changed state. This
bit reflects the state of the P0SERR.DIAG_N bit. To clear this bit, the software must clear the
P0SERR.DIAG_N bit to 0.
Reserved.
© 2011, Texas Instruments Incorporated
Table 16-25.
23 22 21
IPMS PRCS
R/W1C-0 R-0
7 6 5 4
DMPS PCS DPS UFS
R/W1C-0 R-0 R/W1C-0 R-0
Registers
Reserved
R-0
3 2 1
SDBS DSS PSS DHRS
R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0
Serial ATA (SATA) Controller
16
0
1611