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13.1.4.6 PCIe Power/Ground/Termination
Several supplies, grounds, and termination exist to properly power up the PHY.
13.1.4.7 Differential Data Lines
A pair of differential data lines exists, for both transmit and receive paths, for each lane.
13.1.5 Supported Use Case Statement
The PCIe subsystem has only one interface link and this link can be used in a x1 or x2 lane
arrangements connecting to only one single device. In other words, there exists no support for
connecting to two devices in an x1 arrangement since it has the support of a single interface link. It also
means that it can not be used as a switch.
13.1.6 Industry Standard(s) Compliance Statement
The PCIESS complies with the following standards:
•
Revision 2.0 of the PCI Express Base Specification
•
Synopsys DWC PCIe Dual Core Version 3.51a
•
TI SERDES 1.1.03
13.1.7 Terminology Used in this Document
Term
ADPLL
ASPM
AXI
DBI
EP
LVDS
MMR
OCP
OCM
OCMC
PCI
PCIe
PCIESS
PCISIG
PIPE
PME
RC
TC
TLP
VC
VPD
SPRUGX9 – 15 April 2011
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Preliminary
Definition
All Digital Phase Locked Loop
Active state power management
AMBA AXI Bus Protocol
Direct Bus Interface
End Point
Low Voltage Differential Signaling
Memory Mapped Register
Open Core Protocol
On-Chip Memory
On-Chip Memory Controller
Peripheral Component Interconnect
PCI Express
PCI Express subsystem
PCI Special Interest Group
Physical Interface for PCI Express
Power Management Event
Root Complex
Traffic Class
Transaction Layer Packet
Virtual Channel
Vital Product Data
Peripheral Component Interconnect Express (PCIe)
© 2011, Texas Instruments Incorporated
Introduction
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