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Architecture
16.2.4 Transport Layer
The transport layer handles all of the transport layer functions of the SATA protocol. During reception, it
receives a FIS from the Link layer via the Rx FIFO, decodes the type, and routes it to the proper
location via the port DMA. During transmission, it transfers a FIS constructed by the port DMA to the
link layer via the Tx FIFO. It also passes link layer errors and checks for transport layer errors to pass
up to the system.
16.2.5 FIFOs
The transport layer also contains the Tx and Rx FIFOs. These FIFOs are used as asynchronous data
buffers between the serial domain and the bus clock domain. The size of these FIFOs affects the
subsystems ability to buffer data before flow control must be asserted. It also affects the maximum
programmable transaction and burst sizes that can be programmed into the port DMA. The Tx FIFO
size is 64 DWORDS (256 bytes) deep while the Rx FIFO size is 128 DWORDS (512 bytes) deep.
16.2.6 Link Layer
The link layer maintains the link and supports all SATA link layer functionality including:
•
Out-of-band (OOB) transmit signaling
•
Frame negotiation and arbitration
•
Envelope framing/de-framing
•
CRC calculation (receive and transmit)
•
8b/10b encoding/decoding
•
Flow control
•
Frame acknowledgment and status
•
Data width conversion
•
Data scrambling/descrambling
•
Primitive transmission
•
Primitive detection and dropping
•
Power management
16.2.7 PHY
The SATASS includes an integrated TI SERDES macro as a PHY. The PHY handles all of the
serialization/de-serialization, symbol alignment, and Rx OOB signal detection.
16.2.8 Pin Multiplexing
Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package; therefore, some of the SATA controller peripheral signals share SERDES
clock input pins (SERDES_CLKP/N) with the PCI Express peripheral and GPIO Module (GPIO30/31).
Since the same SERDES is used by SATA and PCI Express peripherals, it is recommended the use of
a 100MHz differential input clock source that is ideal for both peripherals. Refer to the device-specific
data manual to determine how pin multiplexing affects the SATA.
16.2.9 Power Management
The SATA controller can be placed in reduced power modes to conserve power during periods of no
activity or no use. The main power management of the peripheral is controlled by the Power, Reset,
and Clock Management (PRCM) unit. The PRCM acts as a master controller for power management of
all of the peripherals on the processor. For detailed information on power management procedures
using the PRCM, see the System Reference Guide.
1570
Serial ATA (SATA) Controller
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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