Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1256

Registers
Table 12-10. McSPI Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions (continued)
Bit Field
2 RX0_FULL
1 TX0_UNDERFLOW
0 TX0_EMPTY
1256
Multichannel Serial Port Interface (McSPI)
Preliminary
Value Description
Receiver register full or almost full. Channel 0. Receiver register full or almost full. Channel
0
Write 0 Event status bit is unchanged.
Read 0 Event false.
Write 1 Event status bit is reset.
Read 1 Event is pending.
Transmitter register underflow. Channel 0.
Write 0 Event status bit is unchanged.
Read 0 Event false.
Write 1 Event status bit is reset.
Read 1 Event is pending.
Transmitter register empty or almost empty. Channel 0. This bit indicate FIFO almost full
status when built-in FIFO is use for transmit register (MCSPI_CH3CONF[FFE0W] is set).
Write 0 Event status bit is unchanged.
Read 0 Event false.
Write 1 Event status bit is reset.
Read 1 Event is pending.
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SPRUGX9 – 15 April 2011
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